Patents by Inventor Jie Xue

Jie Xue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220285003
    Abstract: The techniques described herein relate to computerized methods and apparatus for determining a dose injected into a user by one or more medication delivery devices. Data is accessed that is indicative of an injection event group that includes one or more injection events associated with one or more medication delivery devices. The injection event group is processed to determine the dose injected into the user based on one or more of whether the injection event is associated with a medication delivery device change, a dose size of one or more of the injection events, a position of one or more of the injection events in the injection event group, and/or a time period between one or more injection events to a next injection event in the injection event group.
    Type: Application
    Filed: August 25, 2020
    Publication date: September 8, 2022
    Inventors: Jeffrey Sterling ANDREWS, Xuanyao HE, Jie XUE
  • Publication number: 20220101489
    Abstract: A learning model may provide a hierarchy of convolutional layers configured to perform convolutions upon image features, each layer other than a topmost layer convoluting the image features at a lower resolution to a higher layer, and each layer other than a bottommost layer returning the image features to a lower layer. Each layer fuses the lower resolution image features received from a higher layer with same resolution image features convoluted at the layer, so as to combine large-scale and small-scale features of images. Layers of the hierarchy may be substantially equal to a number of lateral convolutions at a bottommost convolutional layer. The bottommost convolutional layer ultimately passes the fused features to an attention mapping module, which utilizes two attention mapping pathways in combination to detect non-local dependencies and interactions between large-scale and small-scale features of images without de-emphasizing local interactions.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 31, 2022
    Inventors: Dong Nie, Jie Xue, Xiaofeng Ren
  • Patent number: 11119016
    Abstract: A digital image measurement device and method for the surface deformation of specimen based on sub-pixel corner detection is disclosed. This digital image measurement device is composed of a new type of image pressure cell, a complementary metal-oxide-semiconductor (CMOS) camera, a camera bracket, a flexible lens hood, a computer and matching measurement software. This method discretizes the specimen into several four-node finite elements by printing grids on the specimen and takes corners of the grids as the nodes of the finite elements; tracks the deformation of the feature points in real time by edge detection and corner detection based on sub-pixel; captures the deformation of the whole surface of the specimen by the two flat mirrors which are at an 120° angle behind the specimen; achieves the observation of the deformation of the whole surface by conducting splicing and error correction on the three images.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: September 14, 2021
    Assignees: Suzhou H-C Soil & Water Science and Technology Co., Ltd, Dalian University of Technology
    Inventors: Longtan Shao, Xiaoxia Guo, Yonglu Liu, Chuan Huang, Mingming Wu, Xicheng Li, Pingxin Xia, Peng Ju, Xiao Liu, Chun Wang, Jie Xue, Ying Wang
  • Publication number: 20210032374
    Abstract: The present application relates to the field of medicine. The present application relates to an isolated Saposhnikovia divaricata polysaccharide and use thereof in the manufacture of a medicament for treating diabetes mellitus or hyperlipoidemia. In particular, the present application relates to an isolated Saposhnikovia divaricata polysaccharide comprising L-arabinose, D-galacturonic acid, D-mannose, D-glucose and D-galactose, wherein the molar ratio of the L-arabinose: D-galacturonic acid: D-mannose: D-glucose: D-galactose is 1-15:1-10:1-10:10-40:1-15, preferably 1-5:5-10:1-5:20-25:1-5.
    Type: Application
    Filed: February 2, 2019
    Publication date: February 4, 2021
    Inventors: Zhenqing Zhang, Naiyu Xu, Xiang Yin, Li Pang, Lulu Shen, Jie Xue
  • Publication number: 20200376021
    Abstract: Provided herein are an isolated Imperata cylindrica polysaccharide and use thereof in the manufacture of a medicament for treating hyperlipoidemia. The Imperata cylindrica polysaccharide comprises L-arabinose, D-xylose, D-mannose, D-glucose and D-galactose, wherein the molar ratio of the L-arabinose:D-xylose:D-mannose:D-glucose:D-galactose is 1-20:1-15:1-15:15-40:25-60.
    Type: Application
    Filed: February 2, 2019
    Publication date: December 3, 2020
    Inventors: Zhenqing Zhang, Naiyu Xu, Xiang Yin, Li Pang, Lulu Shen, Jie Xue
  • Patent number: 10824026
    Abstract: A substrate and a preparation method thereof, and a display panel are provided. The substrate includes a base substrate. The substrate includes a plurality of units, and a cutting region is between at least two adjacent units; the substrate further includes a first protruding portion, which is on the base substrate and in the cutting region; and a position of the first protruding portion corresponds to a position of an exposure gap measure window of a mask.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: November 3, 2020
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jie Xue, Qian Jiang, Xu Zhang
  • Publication number: 20200264082
    Abstract: A digital image measurement device and method for the surface deformation of specimen based on sub-pixel corner detection is disclosed. This digital image measurement device is composed of a new type of image pressure cell, a complementary metal-oxide-semiconductor (CMOS) camera, a camera bracket, a flexible lens hood, a computer and matching measurement software. This method discretizes the specimen into several four-node finite elements by printing grids on the specimen and takes corners of the grids as the nodes of the finite elements; tracks the deformation of the feature points in real time by edge detection and corner detection based on sub-pixel; captures the deformation of the whole surface of the specimen by the two flat mirrors which are at an 120° angle behind the specimen; achieves the observation of the deformation of the whole surface by conducting splicing and error correction on the three images.
    Type: Application
    Filed: October 18, 2017
    Publication date: August 20, 2020
    Inventors: Longtan SHAO, Xiaoxia GUO, Yonglu LIU, Chuan HUANG, Mingming WU, Xicheng LI, Pingxin XIA, Peng JU, Xiao LIU, Chun WANG, Jie XUE, Ying WANG
  • Publication number: 20190372028
    Abstract: This invention provides a type of Iridium Complexes with molecular formula of L3Ir, together with its application and organic electroluminescent devices, wherein Ir is the central metal atom and L is a ligand. The structure of these complexes is of the following formula (I): Ar is selected from substituted or unsubstituted aryl groups with 6 to 30 carbon atoms, and substituted or unsubstituted heterocyclic aryl groups with 4 to 30 carbon atoms.
    Type: Application
    Filed: December 12, 2017
    Publication date: December 5, 2019
    Applicant: TSINGHUA UNIVERSITY
    Inventors: Juan QIAO, Jie XUE
  • Publication number: 20190146259
    Abstract: The present disclosure provides a substrate and a preparation method thereof, and a display panel. The substrate includes a base substrate. The substrate includes a plurality of units, and a cutting region is between at least two adjacent units; the substrate further comprises a first protruding portion, which is on the base substrate and in the cutting region; and a position of the first protruding portion overlaps a position of an exposure gap measure window of a mask used during the substrate is exposed.
    Type: Application
    Filed: March 6, 2018
    Publication date: May 16, 2019
    Inventors: Jie XUE, Qian JIANG, Xu ZHANG
  • Patent number: 9414497
    Abstract: An apparatus includes a cavity formed in a support structure, the support structure being operable to support a semiconductor device. A circuit element is disposed in the cavity in the support structure, and the cavity in the support structure is filled with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material. The semiconductor device is electrically connected to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: August 9, 2016
    Assignee: Cisco Technology, Inc.
    Inventors: Jovica Savic, Zhiping Yang, Jie Xue, Li Li
  • Publication number: 20150342053
    Abstract: An apparatus includes a cavity formed in a support structure, the support structure being operable to support a semiconductor device. A circuit element is disposed in the cavity in the support structure, and the cavity in the support structure is filled with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material. The semiconductor device is electrically connected to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.
    Type: Application
    Filed: July 31, 2015
    Publication date: November 26, 2015
    Inventors: Jovica Savic, Zhiping Yang, Jie Xue, Li Li
  • Patent number: 9129908
    Abstract: A method and apparatus are provided in which a cavity is formed in a support structure, the support structure being operable to support a semiconductor device, disposing at least a portion of a circuit element in the cavity in the support structure, filling the cavity in the support structure with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material, and electrically connecting the semiconductor device to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: September 8, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Jovica Savic, Zhiping Yang, Jie Xue, Li Li
  • Publication number: 20150173177
    Abstract: A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.
    Type: Application
    Filed: February 23, 2015
    Publication date: June 18, 2015
    Inventors: Mohan R. Nagar, Kuo-Chuan Liu, Mudasir Ahmad, Bangalore J. Shanker, Jie Xue
  • Patent number: 8962388
    Abstract: A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: February 24, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Mohan R. Nagar, Kuo-Chuan Liu, Mudasir Ahmad, Bangalore J. Shanker, Jie Xue
  • Patent number: 8689081
    Abstract: Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: April 1, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Andy Yu, Pierre Chor-Fung Chia, ShiJie Wen, Jie Xue
  • Publication number: 20130139033
    Abstract: Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 30, 2013
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Andy Yu, Pierre Chor-Fung Chia, ShiJie Wen, Jie Xue
  • Publication number: 20130122658
    Abstract: A method and apparatus are provided in which a cavity is formed in a support structure, the support structure being operable to support a semiconductor device, disposing at least a portion of a circuit element in the cavity in the support structure, filling the cavity in the support structure with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material, and electrically connecting the semiconductor device to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 16, 2013
    Applicant: Cisco Technology, Inc.
    Inventors: Jovica Savic, Zhiping Yang, Jie Xue, Li Li
  • Publication number: 20130015557
    Abstract: Circuit elements such as DC blocking capacitors used in communication such as a serial communication link between two or more electrical components are disposed in pre-existing openings in a support structure that supports at least one of the two electrical components. The openings may be plated and used for signal transmission from the one electrical component to a printed circuit board (PCB) supporting the substrate. The DC blocking capacitors may be oriented substantially vertically, and a non-conducting material may be disposed in each opening in the substrate such that the non-conducting material at least partially surrounds and fixes the orientation of the DC blocking capacitor disposed in the opening.
    Type: Application
    Filed: July 13, 2011
    Publication date: January 17, 2013
    Inventors: Zhiping Yang, Jie Xue, Jovica Savic, Li Li
  • Patent number: 8340137
    Abstract: A method and device for performing skew detection on data transmitted over a data channel and a high speed optical communication interface including the device are disclosed, wherein data of a reference frame over a reference channel is composed sequentially of a reference data segment with a length of Umax over each of data channels to be subject to skew detection.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Liang Chen, Yi Jie Xue, Hong Wei Wang, Shu Gong
  • Publication number: 20120113608
    Abstract: A printed circuit board assembly and method of assembly in which underfill is placed between a chip and substrate to support the chip. A trench is formed in the upper layer of the printed circuit board to limit the flow of the underfill and in particular to limit the underfill from contact with adjacent components so that the underfill does not interfere with adjacent components on the printed circuit board assembly.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 10, 2012
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Mohan R. Nagar, Kuo-Chuan Liu, Mudasir Ahmad, Bangalore J. Shanker, Jie Xue