Patents by Inventor Jiebin DUAN

Jiebin DUAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942505
    Abstract: The present invention discloses a pixel structure of a stacked image sensor and a preparation method thereof, by bonding processes to stack a first silicon wafer to a third silicon wafer up and down; wherein, a first photodiode array is set on the first silicon wafer located in middle, and a second photodiode array is provided on the second silicon wafer located above, and the surface of each the second photodiode in the second photodiode array is aligned and bonded correspondingly with the surface of each the first photodiode in the first photodiode array, so as to form a chip of the pixel structure of the stacked image sensor with a very deep junction depth, which is particularly suitable for near-infrared sensitization, and can effectively improve quantum efficiency in near-infrared wave bands; and by adopting a backlight technology, incident lights irradiating to photodiodes are not affected by the metal interconnect layers, both of sensitive and fill factor are high, especially for small-size pixels, whi
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: March 26, 2024
    Assignees: SHANGHAI IC R&D CENTER CO., LTD., CHENGDU IMAGE DESIGN TECHNOLOGY CO. LTD.
    Inventors: Chen Li, Jiebin Duan
  • Publication number: 20230005990
    Abstract: The present invention disclosures a memory array structure, comprising an array composed of multiple memory devices arranged in rows and columns, each of the rows is set with a row leading-out wire, and each of the columns is set with a column leading-out wire, memory devices are correspondingly positioned at intersection points of each row leading-out wire and each column leading-out wire; wherein, the first terminal of each of the memory devices is individually connected to the row leading-out wire of the same row, and the second terminal of each of the memory devices is connected to a first terminal of a switch in the same column, the second terminal of the switch is connected to the column leading-out wire of the same column; wherein, each of the rows is set with one to multiple the switches, and the first terminal of each of the switches is connected to one to all of the second terminals of the memory devices in the same column.
    Type: Application
    Filed: July 23, 2020
    Publication date: January 5, 2023
    Inventors: Ling Shen, Yu Jiang, Huijie Yan, Zhifang Li, Linmei Dong, Jiebin Duan, Jianxin Wen
  • Publication number: 20220399237
    Abstract: The present invention disclosures a critical dimension error analysis method, comprising: S01: performing lithography processes on a wafer, measuring the critical dimension (CD) values of the test points in each of the fields respectively; M and N are integers greater than 1; S02: removing extreme outliers from the critical dimension (CD) values; S03: rebuilding remaining CD values by a reconstruction model fitting method, and obtaining rebuilt critical dimension (CD?) values, according to relative error between CD? and CD, dividing the rebuilt critical dimension (CD?) values into scenes and the number of the scenes is A; S04: calculating components and corresponding residuals of the test points in each of the scenes under a reference system corresponding to a correction model by parameter estimation; S05: modifying machine parameters and masks by the correction model according to above calculation results.
    Type: Application
    Filed: July 23, 2020
    Publication date: December 15, 2022
    Inventors: Xueru YU, Hongxia SUN, Chen LI, Pengfei WANG, Jiebin DUAN, Xiucui WANG, Hao FU, Tao ZHOU, Yan YAN, Bowen XU, Lingyi GUO, Liren LI
  • Patent number: 11418738
    Abstract: The present invention discloses an image sensor for real-time calibration of dark current, including a pixel array comprises at least a pixel unit, the pixel unit includes a pixel photosensitive portion, a pixel dark shielding portion and a subtraction circuit, photodiodes in the pixel photosensitive portion and the pixel dark shielding portion are isolated by deep trench isolations, the pixel dark shielding portion are covered by a dark shielding layer; both of the pixel photosensitive portion and the pixel dark shielding portion adopt a same voltage and sequential control, a light ambient voltage signal and a non-light ambient voltage signal are generated and connected to both ends of a subtraction circuit to realize subtraction and dark current calibration.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: August 16, 2022
    Assignees: SHANGHAI IC R&D CENTER CO., LTD, CHENGDU IMAGE DESIGN TECHNOLOGY CO., LTD.
    Inventors: Jiebin Duan, Chen Li, Pengfei Wang, Tao Zhou
  • Publication number: 20210408100
    Abstract: The present invention discloses a pixel structure of a stacked image sensor and a preparation method thereof, by bonding processes to stack a first silicon wafer to a third silicon wafer up and down; wherein, a first photodiode array is set on the first silicon wafer located in middle, and a second photodiode array is provided on the second silicon wafer located above, and the surface of each the second photodiode in the second photodiode array is aligned and bonded correspondingly with the surface of each the first photodiode in the first photodiode array, so as to form a chip of the pixel structure of the stacked image sensor with a very deep junction depth, which is particularly suitable for near-infrared sensitization, and can effectively improve quantum efficiency in near-infrared wave bands; and by adopting a backlight technology, incident lights irradiating to photodiodes are not affected by the metal interconnect layers, both of sensitive and fill factor are high, especially for small-size pixels, whi
    Type: Application
    Filed: August 7, 2019
    Publication date: December 30, 2021
    Inventors: Chen LI, Jiebin DUAN
  • Patent number: 10939059
    Abstract: The present disclosure provides a global shutter CMOS pixel circuit and its image capturing method. The global shutter CMOS pixel circuit comprising a power supply unit, a pixel signal generating unit, a signal sampling and holding unit and a signal outputting unit. An output of the pixel signal generating unit is connected to an input of the signal sampling and holding unit. An output of the signal sampling and holding unit is connected to an input of the signal outputting unit. The output signal of the pixel and the photo-generated current are set to a logarithmic relationship, which effectively increases the signal dynamic range. Therefore, image signal transmission with high speed and high dynamic range can be achieved simultaneously. Furthermore, the pixels in the present disclosure can eliminate the process variations, which increases the consistency of the pixels.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: March 2, 2021
    Assignees: SHANGHAI IC R&D CENTER CO., LTD, CHENGDU IMAGE DESIGN TECHNOLOGY CO. LTD.
    Inventors: Jiebin Duan, Zheng Ren, Yu Jiang, Jianxin Wen, Changming Pi
  • Publication number: 20210058574
    Abstract: The present invention discloses an image sensor for real-time calibration of dark current, including a pixel array comprises at least a pixel unit, the pixel unit includes a pixel photosensitive portion, a pixel dark shielding portion and a subtraction circuit, photodiodes in the pixel photosensitive portion and the pixel dark shielding portion are isolated by deep trench isolations, the pixel dark shielding portion are covered by a dark shielding layer; both of the pixel photosensitive portion and the pixel dark shielding portion adopt a same voltage and sequential control, a light ambient voltage signal and a non-light ambient voltage signal are generated and connected to both ends of a subtraction circuit to realize subtraction and dark current calibration.
    Type: Application
    Filed: August 29, 2018
    Publication date: February 25, 2021
    Inventors: Jiebin DUAN, Chen LI, Pengfei WANG, Tao ZHOU
  • Publication number: 20200007801
    Abstract: The present disclosure provides a global shutter CMOS pixel circuit and its image capturing method. The global shutter CMOS pixel circuit comprising a power supply unit, a pixel signal generating unit, a signal sampling and holding unit and a signal outputting unit. An output of the pixel signal generating unit is connected to an input of the signal sampling and holding unit. An output of the signal sampling and holding unit is connected to an input of the signal outputting unit. The output signal of the pixel and the photo-generated current are set to a logarithmic relationship, which effectively increases the signal dynamic range. Therefore, image signal transmission with high speed and high dynamic range can be achieved simultaneously. Furthermore, the pixels in the present disclosure can eliminate the process variations, which increases the consistency of the pixels.
    Type: Application
    Filed: November 22, 2017
    Publication date: January 2, 2020
    Inventors: Jiebin DUAN, Zheng REN, Yu JIANG, Jianxin WEN, Changming PI