Abstract: The present disclosure provides a method for fabricating an anti-reflective layer on a quartz surface by using a metal-induced self-masking etching technique, comprising: performing reactive ion etching to a metal material and a quartz substrate by using a mixed gas containing a fluorine-based gas, wherein metal atoms and/or ions of the metal material are sputtered to a surface of the quartz substrate, to form a non-volatile metal fluoride on the surface of the quartz substrate; forming a micromask by a product of etching generated by reactive ion etching gathering around the non-volatile metal fluoride; and etching the micromask and the quartz substrate simultaneously, to form an anti-reflective layer having a sub-wavelength structure.

Abstract: The present disclosure provides a memristor, including a transistor and a resistive random access memory, where a drain electrode of the transistor is connected to a bottom electrode of the resistive random access memory; and the resistive random access memory includes: the bottom electrode, a resistive random access material layer, a current compliance layer and a top electrode from bottom to top, where the current compliance layer is configured to stabilize a fluctuation of a low resistance by reducing a surge current and optimizing a heat distribution, so as to improve a calculation accuracy of a Hamming distance.

Abstract: The present disclosure provides a method for fabricating an anti-reflective layer on a quartz surface by using a metal-induced self-masking etching technique, comprising: performing reactive ion etching to a metal material and a quartz substrate by using a mixed gas containing a fluorine-based gas, wherein metal atoms and/or ions of the metal material are sputtered to a surface of the quartz substrate, to form a non-volatile metal fluoride on the surface of the quartz substrate; forming a micromask by a product of etching generated by reactive ion etching gathering around the non-volatile metal fluoride; and etching the micromask and the quartz substrate simultaneously, to form an anti-reflective layer having a sub-wavelength structure.

Abstract: A defect detection system for an extreme ultraviolet lithography mask comprises an extreme ultraviolet light source (1), extreme ultraviolet light transmission parts (2, 3), an extreme ultraviolet lithography mask (4), a photon sieve (6) and a collection (7) and analysis (8) system. Point light source beams emitted by the extreme ultraviolet light source (1) are focused on the extreme ultraviolet lithography mask (4) through the extreme ultraviolet light transmission parts (2, 3); the extreme ultraviolet lithography mask (4) emits scattered light and illuminates the photon sieve (6); and the photon sieve (6) forms a dark field image and transmits the same to the collection (7) and analysis (8) system. The defect detection system for the extreme ultraviolet photolithographic mask uses the photon sieve to replace a Schwarzchild objective, thereby realizing lower cost, relatively small size and high resolution.

Abstract: The present disclosure provides a method for manufacturing ordered nanowires array of NiO doped with Pt in situ, comprising: growing a Ni layer on a high-temperature resistant and insulated substrate; applying a photoresist on the Ni layer, pattering a pattern region of the ordered nanowires array by applying electron beam etching on the photoresist, growing Ni on the pattern region of the ordered nanowires array, peeling off the photoresist by acetone and etching the surface of the Ni layer by ion beam etching so as to etch off the Ni layer grown on the surface of the substrate and to leave the Ni on the pattern region of the ordered nanowires array to form the ordered Ni nanowires array; dipping the ordered Ni nanowires array into a solution of H2PtCl6 so as to displace Pt on the Ni nanowires array by a displacement reaction; and oxidizing the Ni nanowires array attached with Pt in an oxidation oven to obtain the ordered nanowires array of NiO doped with Pt.

Abstract: The present disclosure provides a method for manufacturing ordered nanowires array of NiO doped with Pt in situ, comprising: growing a Ni layer on a high-temperature resistant and insulated substrate; applying a photoresist on the Ni layer, pattering a pattern region of the ordered nanowires array by applying electron beam etching on the photoresist, growing Ni on the pattern region of the ordered nanowires array, peeling off the photoresist by acetone and etching the surface of the Ni layer by ion beam etching so as to etch off the Ni layer grown on the surface of the substrate and to leave the Ni on the pattern region of the ordered nanowires array to form the ordered Ni nanowires array; dipping the ordered Ni nanowires array into a solution of H2PtCl6 so as to displace Pt on the Ni nanowires array by a displacement reaction; and oxidizing the Ni nanowires array attached with Pt in an oxidation oven to obtain the ordered nanowires array of NiO doped with Pt.

Abstract: A defect detection system for an extreme ultraviolet lithography mask comprises an extreme ultraviolet light source (1), extreme ultraviolet light transmission parts (2, 3), an extreme ultraviolet lithography mask (4), a photon sieve (6) and a collection (7) and analysis (8) system. Point light source beams emitted by the extreme ultraviolet light source (1) are focused on the extreme ultraviolet lithography mask (4) through the extreme ultraviolet light transmission parts (2, 3); the extreme ultraviolet lithography mask (4) emits scattered light and illuminates the photon sieve (6); and the photon sieve (6) forms a dark field image and transmits the same to the collection (7) and analysis (8) system. The defect detection system for the extreme ultraviolet photolithographic mask uses the photon sieve to replace a Schwarzchild objective, thereby realizing lower cost, relatively small size and high resolution.

Abstract: The present disclosure relates to the microelectronics field, and particularly, to a metal oxide resistive switching memory and a method for manufacturing the same. The method may comprise: forming a W-plug lower electrode above a MOS device; sequentially forming a cap layer, a first dielectric layer, and an etching block layer on the W-plug lower electrode; etching the etching block layer, the first dielectric layer, and the cap layer to form a groove for a first level of metal wiring; sequentially forming a metal oxide layer, an upper electrode layer, and a composite layer of a diffusion block layer/a seed copper layer/a plated copper layer in the groove for the first level of metal wiring; patterning the upper electrode layer and the composite layer by CMP, to form a memory cell and the first level of metal wiring in the groove in the first dielectric layer; and performing subsequent processes to complete the metal oxide resistive switching memory.

Abstract: The present disclosure relates to the microelectronics field, and particularly, to a metal oxide resistive switching memory and a method for manufacturing the same. The method may comprise: forming a W-plug lower electrode above a MOS device; sequentially forming a cap layer, a first dielectric layer, and an etching block layer on the W-plug lower electrode; etching the etching block layer, the first dielectric layer, and the cap layer to form a groove for a first level of metal wiring; sequentially forming a metal oxide layer, an upper electrode layer, and a composite layer of a diffusion block layer/a seed copper layer/a plated copper layer in the groove for the first level of metal wiring; patterning the upper electrode layer and the composite layer by CMP, to form a memory cell and the first level of metal wiring in the groove in the first dielectric layer; and performing subsequent processes to complete the metal oxide resistive switching memory.