Abstract: A memory device includes a stacked structure. The stacked structure includes a plurality of interlayer dielectric layers and a gate structure between adjacent interlayer dielectric layers. A charge trapping layer and a blocking layer are between the adjacent interlayer dielectric layers. The blocking layer envelops the charge trapping layer and separates the charge trapping layer from the gate structure. A tunneling layer is disposed along a sidewall of the stacked structure and in contact with each of the gate structure and the charge trapping layer. A channel layer is disposed on a sidewall of the tunneling layer.

Abstract: A method for fabricating a memory device includes providing an initial semiconductor structure, including a base substrate, a stack structure of interlayer dielectric layers and first sacrificial layers; a channel trench formed through the stack structure. The method includes removing a portion of each first sacrificial layer from the channel trench to form a trapping-layer trench; forming a second sacrificial layer in the trapping-layer trench; forming a charge trapping film to fill the trapping-layer trench; and removing a portion of the charge trapping film from the channel trench to form a charge trapping layer; forming a tunneling layer and a channel layer on the sidewalls of the channel trench; removing the first sacrificial layers and the second sacrificial layer; forming a blocking layer on the charge trapping layer; and forming gate structures, in contact with the tunneling layer, between adjacent interlayer dielectric layers.

Abstract: A method for fabricating a memory device includes providing an initial semiconductor structure, including a base substrate, a stack structure of interlayer dielectric layers and first sacrificial layers; a channel trench formed through the stack structure. The method includes removing a portion of each first sacrificial layer from the channel trench to form a trapping-layer trench; forming a second sacrificial layer in the trapping-layer trench; forming a charge trapping film to fill the trapping-layer trench; and removing a portion of the charge trapping film from the channel trench to form a charge trapping layer; forming a tunneling layer and a channel layer on the sidewalls of the channel trench; removing the first sacrificial layers and the second sacrificial layer; forming a blocking layer on the charge trapping layer; and forming gate structures, in contact with the tunneling layer, between adjacent interlayer dielectric layers.