Patents by Inventor Jiejie Lv

Jiejie Lv has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Phase locked loop frequency calibration circuit and method
    Patent number: 9698799
    Abstract: A phase locked loop frequency calibration circuit and a method are provided. The circuit includes a timer, a counter, a control module, a frequency divider and a voltage controlled oscillator; output of voltage controlled oscillator is connected with first input of frequency divider, output of frequency divider is connected with first input of counter, second input of frequency divider, first input of timer and second input of counter are respectively connected with first output of control module, third input of counter is connected with output of timer, output of counter is connected with first input of control module, a reference clock signal is respectively sent to second input of timer and second input of control module, the number of clocks used by frequency divider to perform frequency division on output clock signal of voltage controlled oscillator is sent to third input of control module.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: July 4, 2017
    Assignee: SHANGHAI EASTSOFT MICROELECTRONICS CO., LTD.
    Inventors: Ruijin Liu, Xu Zhang, Jingjing Tao, Jiejie Lv
  • PHASE LOCKED LOOP FREQUENCY CALIBRATION CIRCUIT AND METHOD
    Publication number: 20160308542
    Abstract: A phase locked loop frequency calibration circuit and a method are provided. The circuit includes a timer, a counter, a control module, a frequency divider and a voltage controlled oscillator; output of voltage controlled oscillator is connected with first input of frequency divider, output of frequency divider is connected with first input of counter, second input of frequency divider, first input of timer and second input of counter are respectively connected with first output of control module, third input of counter is connected with output of timer, output of counter is connected with first input of control module, a reference clock signal is respectively sent to second input of timer and second input of control module, the number of clocks used by frequency divider to perform frequency division on output clock signal of voltage controlled oscillator is sent to third input of control module.
    Type: Application
    Filed: June 23, 2016
    Publication date: October 20, 2016
    Inventors: Ruijin Liu, Xu Zhang, Jingjing Tao, Jiejie Lv