Patents by Inventor Jieon Yoon

Jieon Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12209916
    Abstract: The present invention relates to a composition for temperature sensors including graphene oxide, DNAzyme and PNA, a temperature sensing method and a kit using the same. In the present invention, when the DNAzyme/PNA duplex is dissociated at a certain temperature, graphene oxide adsorbs PNA with excellent selectivity and irreversibility, enabling recall of temperature, to permit delayed color development in the time of need. Also, the target temperature can be easily and quickly detected with the naked eye through the color change of the colorimetric reagent, and the thermosensor is technically convenient and easy to apply, so it can be used in various biological applications. Moreover, it can be used as a barcode (on/off) system using a combination of PNA probes with various lengths, and thus can be broadly applied to sensing a diverse range of temperatures.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: January 28, 2025
    Assignee: Korea Research Institute of Chemical Technology
    Inventors: Jieon Lee, Woo-keun Kim, Seokjoo Yoon
  • Publication number: 20170271479
    Abstract: A method of fabricating a semiconductor device is provided as follows. A source/drain pattern is formed on a substrate. The source/drain pattern contains silicon atoms and germanium atoms. At least one germanium atom is removed from the germanium atoms of the source/drain pattern.
    Type: Application
    Filed: June 2, 2017
    Publication date: September 21, 2017
    Inventors: JINBUM KIM, JAEYOUNG PARK, DONGHUN LEE, JEONGHO YOO, JIEON YOON, KWAN HEUM LEE, CHOEUN LEE, BONYOUNG KOO
  • Patent number: 9698244
    Abstract: A method of fabricating a semiconductor device is provided as follows. A source/drain pattern is formed on a substrate. The source/drain pattern contains silicon atoms and germanium atoms. At least one germanium atom is removed from the germanium atoms of the source/drain pattern.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: July 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinbum Kim, Jaeyoung Park, Donghun Lee, Jeongho Yoo, Jieon Yoon, Kwan Heum Lee, Choeun Lee, Bonyoung Koo
  • Patent number: 9530870
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a gate pattern on a semiconductor substrate, injecting amorphization elements into the semiconductor substrate to form an amorphous portion at a side of the gate pattern, removing the amorphous portion to form a recess region, and forming a source/drain pattern in the recess region. When the recess region is formed, an etch rate of the amorphous portion is substantially the same in two different directions (e.g., <111> and any other direction) of the semiconductor substrate.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: December 27, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jieon Yoon, Seokhoon Kim, Gyeom Kim, Nam-Kyu Kim, JinBum Kim, Dong Chan Suh, Kwan Heum Lee, Byeongchan Lee, Choeun Lee, Sujin Jung
  • Publication number: 20160300929
    Abstract: A method of fabricating a semiconductor device is provided as follows. A source/drain pattern is formed on a substrate. The source/drain pattern contains silicon atoms and germanium atoms. At least one germanium atom is removed from the germanium atoms of the source/drain pattern.
    Type: Application
    Filed: March 7, 2016
    Publication date: October 13, 2016
    Inventors: JINBUM KIM, Jaeyoung Park, Donghun Lee, Jeongho Yoo, Jieon Yoon, Kwan Heum Lee, Choeun Lee, Bonyoung Koo
  • Publication number: 20160027902
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes forming a gate pattern on a semiconductor substrate, injecting amorphization elements into the semiconductor substrate to form an amorphous portion at a side of the gate pattern, removing the amorphous portion to form a recess region, and forming a source/drain pattern in the recess region. When the recess region is formed, an etch rate of the amorphous portion is substantially the same in two different directions (e.g., <111> and any other direction) of the semiconductor substrate.
    Type: Application
    Filed: July 22, 2015
    Publication date: January 28, 2016
    Inventors: Jieon Yoon, Seokhoon Kim, Gyeom Kim, Nam-Kyu Kim, JinBum Kim, Dong Chan Suh, Kwan Heum Lee, Byeongchan Lee, Choeun Lee, Sujin Jung