Patents by Inventor Jieping ZHANG
Jieping ZHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162134Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.Type: ApplicationFiled: January 19, 2024Publication date: May 16, 2024Inventors: Xiao LU, Jiongxin LU, Christopher COMBS, Alexander HUETTIS, John HARPER, Jieping ZHANG, Nachiket R. RARAVIKAR, Pramod MALATKAR, Steven A. KLEIN, Carl DEPPISCH, Mohit SOOD
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Publication number: 20240096809Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein.Type: ApplicationFiled: September 15, 2022Publication date: March 21, 2024Applicant: Intel CorporationInventors: Hiroki Tanaka, Robert Alan May, Onur Ozkan, Ali Lehaf, Steve Cho, Gang Duan, Jieping Zhang, Rahul N. Manepalli, Ravindranath Vithal Mahajan, Hamid Azimi
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Patent number: 11916003Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.Type: GrantFiled: September 18, 2019Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: Xiao Lu, Jiongxin Lu, Christopher Combs, Alexander Huettis, John Harper, Jieping Zhang, Nachiket R. Raravikar, Pramod Malatkar, Steven A. Klein, Carl Deppisch, Mohit Sood
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Publication number: 20210082798Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.Type: ApplicationFiled: September 18, 2019Publication date: March 18, 2021Inventors: Xiao LU, Jiongxin LU, Christopher COMBS, Alexander HUETTIS, John HARPER, Jieping ZHANG, Nachiket R. RARAVIKAR, Pramod MALATKAR, Steven A. KLEIN, Carl DEPPISCH, Mohit SOOD
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Patent number: 10049971Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.Type: GrantFiled: April 3, 2017Date of Patent: August 14, 2018Assignee: Intel CorporationInventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
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Publication number: 20170207152Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.Type: ApplicationFiled: April 3, 2017Publication date: July 20, 2017Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
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Patent number: 9613933Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.Type: GrantFiled: March 5, 2014Date of Patent: April 4, 2017Assignee: Intel CorporationInventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jr., Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
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Patent number: 9508610Abstract: A method including emitting a terahertz beam from a light source at a layer of molding material; detecting a reflectance of the beam; and determining a thickness of the layer of molding material. A system including a panel supporter operable to support a panel including a plurality of substrates arranged in a planar array; a light source operable to emit a terahertz beam at a panel on the panel supporter; a detector operable to detect a reflection of a terahertz beam emitted at a panel; and a processor operable to determine a thickness of a material on the panel based on a time delay for an emitted terahertz beam to be detected by the detector.Type: GrantFiled: September 27, 2014Date of Patent: November 29, 2016Assignee: Intel CorporationInventors: Shuhong Liu, Nilanjan Z. Ghosh, Zhiyong Wang, Deepak Goyal, Shripad Gokhale, Jieping Zhang
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Publication number: 20160093540Abstract: A method including emitting a terahertz beam from a light source at a layer of molding material; detecting a reflectance of the beam; and determining a thickness of the layer of molding material. A system including a panel supporter operable to support a panel including a plurality of substrates arranged in a planar array; a light source operable to emit a terahertz beam at a panel on the panel supporter; a detector operable to detect a reflection of a terahertz beam emitted at a panel; and a processor operable to determine a thickness of a material on the panel based on a time delay for an emitted terahertz beam to be detected by the detector.Type: ApplicationFiled: September 27, 2014Publication date: March 31, 2016Inventors: Shuhong LIU, Nilanjan Z. GHOSH, Zhiyong WANG, Deepak GOYAL, Shripad GOKHALE, Jieping ZHANG
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Publication number: 20150255415Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.Type: ApplicationFiled: March 5, 2014Publication date: September 10, 2015Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, JR., Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin