Patents by Inventor Jieqin ZHANG

Jieqin ZHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10600766
    Abstract: A dual-channel heat-conducting encapsulation structure of a solid-state phosphor integrated light source has a solid-state phosphor, a transparent organic silica gel, LED chips and a substrate. The LED chips are arranged on the substrate. The dual-channel heat-conducting encapsulation structure also has heat-conducting columns fixed on the substrate, and the heat-conducting columns are disposed away from the LED chips; the solid-state phosphor is placed on the heat-conducting columns without contacting the LED chips; the transparent organic silica gel is filled in the gap between the solid-state phosphor and the substrate. By adopting the design of double heat-conducting channels, separates two heat sources of the LED light source to sufficiently conduct the heat, the heat of the solid-state phosphor and the LED chips reaches the substrate through the respective channels, and then is transferred from the substrate through the heat sink into the atmosphere.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: March 24, 2020
    Assignee: FUJIAN CAS-CERAMIC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Shanghui Ye, Jieqin Zhang, Maochun Hong, Wenxiong Lin, Wang Guo, Yunfeng Zhang
  • Patent number: 10504875
    Abstract: A die-bonding substrate has a substrate, and a conductive line layer and a chip array provided on the substrate. The conductive line layer includes a chip welding wire region and an external electrode region connected with each other. The chip welding wire region is composed of multiple conductive lines, wherein the central conductive line located in the central position of the chip welding wire region is a straight line section. The conductive lines arranged at both sides of the central conductive line are straight line sections at both ends, and arc sections curved outwards in the middle, so that the entire chip welding wire region forms a circular area. The array chips are arranged inside the circular area, and are electrically connected with the conductive lines arranged at both sides. The entire chip welding wire region can also form a rectangular area.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: December 10, 2019
    Assignee: FUJIAN CAS-CERAMIC OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventors: Shanghui Ye, Jieqin Zhang, Maochun Hong, Wenxiong Lin, Wang Guo, Yunfeng Zhang
  • Publication number: 20180358333
    Abstract: A dual-channel heat-conducting encapsulation structure of a solid-state phosphor integrated light source has a solid-state phosphor, a transparent organic silica gel, LED chips and a substrate. The LED chips are arranged on the substrate. The dual-channel heat-conducting encapsulation structure also has heat-conducting columns fixed on the substrate, and the heat-conducting columns are disposed away from the LED chips; the solid-state phosphor is placed on the heat-conducting columns without contacting the LED chips; the transparent organic silica gel is filled in the gap between the solid-state phosphor and the substrate. By adopting the design of double heat-conducting channels, separates two heat sources of the LED light source to sufficiently conduct the heat, the heat of the solid-state phosphor and the LED chips reaches the substrate through the respective channels, and then is transferred from the substrate through the heat sink into the atmosphere.
    Type: Application
    Filed: June 8, 2016
    Publication date: December 13, 2018
    Inventors: Shanghui YE, Jieqin ZHANG, Maochun HONG, Wenxiong LIN, Wang GUO, Yunfeng ZHANG
  • Publication number: 20180315739
    Abstract: A die-bonding substrate has a substrate, and a conductive line layer and a chip array provided on the substrate. The conductive line layer includes a chip welding wire region and an external electrode region connected with each other. The chip welding wire region is composed of multiple conductive lines, wherein the central conductive line located in the central position of the chip welding wire region is a straight line section. The conductive lines arranged at both sides of the central conductive line are straight line sections at both ends, and arc sections curved outwards in the middle, so that the entire chip welding wire region forms a circular area. The array chips are arranged inside the circular area, and are electrically connected with the conductive lines arranged at both sides. The entire chip welding wire region can also form a rectangular area.
    Type: Application
    Filed: June 8, 2016
    Publication date: November 1, 2018
    Inventors: Shanghui YE, Jieqin ZHANG, Maochun HONG, Wenxiong LIN, Wang GUO, Yunfeng ZHANG