Patents by Inventor Jieren Xie

Jieren Xie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080315412
    Abstract: The invention discloses a novel package structure of integrate circuit or discrete device and packaging method, and includes the lead pins adjacent to the island; another metal layer formed at the bottom of the island; another metal layer formed at the bottom of lead pins; chip mounted on the island; wires bonded between the chip and the lead pins; the molded body encapsulating the top surface and side surface of the island and the lead pins, small protrusions of the island and the lead pins below the molded body; in the individual package, the number of the island can be one or more, lead pins can be arrayed at one side of the island, also can be arrayed at two sides or three sides of the island, one or two rows of lead pins can be located around the island. The invention provides strong welding, good quality, low cost, smooth production, wide applicability, flexible arrangement of the chips.
    Type: Application
    Filed: April 6, 2006
    Publication date: December 25, 2008
    Applicant: Jiangsu Changjiang Electronics Technology Co., Ltd
    Inventors: Jerry Liang, Jieren Xie, Xinchao Wang, Xiekang Yu, Yujuan Tao, Rongfu Wen, Fushou Li, Zhengwei Zhou, Da Wang, Haibo Ge, Qiang Zheng, Zhen Gong, Weijun Yang
  • Publication number: 20080285251
    Abstract: A packaging substrate with fiat bumps for an electronic device and a method of manufacturing the same relate to the production of the packaging substrate for an electronic device, which comprises base islands and pins structurally and wherein the base islands and pins which all exhibit flat bump shape distribute on the front face of the substrate; the bottom side of the bumps, namely the rear faces of the base islands and pins are contiguous in the same substrate; in the packaging body of a single electronic device to be formed in later procedure, one or more base island may be included, the pins may arrange on one single side of the base island, also may arrange on the both sides or three sides of the base island, or may surround the base island so as to form the structure of one or more circuits of pins.
    Type: Application
    Filed: April 6, 2006
    Publication date: November 20, 2008
    Applicant: Jiangsu Changiang Electronics Technology Co., Ltd.
    Inventors: Jerry Liang, Jieren Xie, Xinchao Wang, Xiekang Yu, Yujuan Tao, Rongfu Wen, Fushou Li, Zhengwei Zhou, Da Wang, Haibo Ge, Qiang Zheng, Zhen Gong, Weijun Yang
  • Publication number: 20080258273
    Abstract: The invention discloses an ultra thin package structure of leadless electronic device and the packaging method, and includes lead support base adjacent to the chip support base; chip mounted on the chip support base; wires bonded between chip and lead support base; the molded body encapsulating the top surface and side surface of the chip support base, small protrusions of the chip support base and lead support base below the molded body; in the individual package, the number of the chip support base island can be one or more, the lead pins can be arrayed at one side of the island, also can be arrayed at two sides or three sides of the island, one or two rows of lead pins can be located around the island.
    Type: Application
    Filed: April 6, 2006
    Publication date: October 23, 2008
    Applicant: Jiangsu Changjiang Electronics Technology Co., Ltd
    Inventors: Jerry Liang, Jieren Xie, Xinchao Wang, Xiekang Yu, Yujuan Tao, Rongfu Wen, Fushou Li, Zhengwei Zhou, Da Wang, Haibo Ge, Qiang Zheng, Zhen Gong, Weijun Yang