Abstract: The present invention discloses a method for integrating a vertical nanowire transistor and belongs to a field of field effect transistor logic device in a CMOS ultra-large scale integrated circuit (ULSI). The method realizes the integration of the vertical-nanowire transistor by combining selective epitaxy and replacement gate on sidewall. In comparison with an existing method for forming a vertical nanowire channel by etching, a size and shape of a cross section of a device channel can be accurately controlled, a consistency of device characteristic can be improved, and an etching damage during the forming of a channel in the existing method can be avoided, thereby the device performance can be improved.

Abstract: Disclosed herein is a method for fabricating a FinFET with separated double gates on a bulk silicon, comprising: forming a pattern for a source, a drain and a thin bar connecting the source and the drain; forming an oxidation isolation layer; forming a gate structure and a source/drain structure; and forming a metal contact and a metal interconnection. By means of the method herein, it is very easy to fabricate the FinFET with separated double gates on the bulk silicon wafer, and the overall process flow is completely compatible with the conventional silicon-based very large scale integrated circuit manufacturing technology. Thus, the method herein is simple, convenient and has a short process period, greatly economizing the cost of the silicon wafer. In addition, by employing the FinFET with separated double gates fabricated by the method according to the invention, the short channel effect can be effectively suppressed.

Abstract: The present invention discloses a method for preparing a nano-scale field-effect transistor, and belongs to the field of large-scale integrated circuit manufacturing technologies. The method focuses on preparing a nano-scale field-effect transistor on an SOI substrate by epitaxial growth. In the invention, the material and appearance of a channel of a nano-scale device may be accurately controlled by using an epitaxy process, and the device performance may be further optimized; moreover, a threshold voltage may be flexibly adjusted to adapt for requirements of different IC designs by realizing different channel doping types and doping concentrations; also, a gate structure with a consistent width in a height direction may be obtained, the parasitism and fluctuation of the device may be reduced, and at the same time, the method can be well compatible with CMOS post-gate processes, and is simple in procedure and low in cost.

Abstract: The present invention discloses a method for fabricating a quasi SOI source-drain multi-gate device, belonging to a field of manufacturing ultra large scale integrated circuit, the method comprises in sequence the following steps of: forming a Fin strip-shaped active region on a first semiconductor substrate; forming a STI isolation layer; depositing a gate dielectric layer and a gate material layer, forming a gate stack structure; forming a doped structure of a source-drain extension region; forming a recessed source-drain structure; forming a quasi SOI source-drain isolation layer; in-situ doping an epitaxial source and drain of a second semiconductor material and performing annealing for activating; removing a dummy gate and performing a deposition of a high k metal gate again; and forming a contact and a metal interconnection.

Abstract: A method for fabricating multiple layers of ultra narrow silicon wires comprises the steps of fabricating wet-etch masking layers of silicon; forming a Fin and source/drain regions located at both ends thereof by epitaxy; forming the multiple layers of ultra narrow silicon wires. The present invention has advantages in that: the atom layer depositing may define the position of the ultra narrow silicon wires accurately, having a good controllability; the anisotropic wet-etch for silicon is performed in a self-stop manner and has a large process window, so that the cross-section shape of the nanowires formed by wet-etch is uniform and smooth.

Abstract: Disclosed is a semiconductor structure, comprising: a semiconductor substrate and multilayer superfine silicon lines, wherein a profile shape of each of the multilayer superfine silicon lines is controlled dually by a crystal orientation of the substrate and an axial crystal orientation of the line. Also disclosed is a method of forming the same comprises: forming a fin-shaped silicon island (Fin) and a source-drain region on the two ends thereof via an etching process; preparing a corrosion shielding layer for silicon; and forming multilayer superfine silicon lines. The invention has the following advantages: the locations and the sectional shapes of the multilayer superfine silicon lines finally formed are uniform and controllable; the anisotropic corrosion for silicon stop automatically, the process window is large, and silicon lines with different diameters may be achieved from the same silicon wafer.

Abstract: The present invention discloses a method of adjusting a threshold voltage of a multi-gate structure device, wherein, preparing the multi-gate structure device to be formed to have a channel impurity distribution with high doping on surface and lowly doping inside, where while a threshold voltage is adjusted by using impurity doping, the influences of the Coulomb impurity scattering on the carriers is reduced as much as possible, so that the mobility of the carriers is maintained at a higher level. Firstly, the present solution is able to make a multi-gate device obtain a larger range of a multi-threshold voltage; it is convenient for the various demands of the device in the circuit designing by IC designers.

Abstract: A method for preparing a multilayer superfine silicon line, comprising: preparing an etching masking layer of silicon; forming a fin and source/drain region on both ends thereof by epitaxy; and forming a multilayer superfine silicon line. The method has the following advantages: the atom layer deposition accurately defines the position of the superfine line, giving good controllability; the anisotropic etching of the silicon is automatically stopped, so the process window is large, and the cross section of a nanowire obtained via etching is uniform and flat; a method of mask preparation before channel epitaxy is employed to provide a simple process of forming a multilayer sidewall etching mask, i.e., the multilayer sidewall mask is obtained by etching an epitaxial window only once irrespective of the number of masking layers; a line having a size less than 10 nm can be prepared in conjunction with oxidation technology, thus satisfying the requirement of the key process of a small-sized device.

Abstract: A method for fabricating a multi-gate structure device with a source and a drain having a quasi-SOI structure, comprising forming an active region in a shape of a fin bar, forming an oxide isolation layer for shallow trench isolation (STI), forming a polysilicon dummy gate, forming source and drain extension regions, forming the source and the drain with the quasi-SOI structure, and forming a high-K metal gate. Solution(s) consistent with the present innovations may be achieved by using a process method compatible with the conventional bulk silicon CMOS processes and can be easily integrated into the process flow. Moreover, innovations here may provide a small leakage current even in a case of having a short channel length, thereby reducing the power consumption of the device.

Abstract: The present invention discloses a method for fabricating a quasi-SOI source/drain field effect transistor device, which comprises the steps of forming an active region of the device; forming a gate stack structure of the device; doping a source/drain extension region, and forming a first layer of side wall at two sides of the gate stack structure; forming a recessed source/drain structure; forming a quasi-SOI source/drain isolation layer; in-situ doping an epitaxial second semiconductor material source/drain, and activating by annealing; removing the previous dummy gate and re-depositing a high-k metal gate, if a post-gate process is employed; and forming contacts and metal interconnections.

Abstract: The present invention discloses a method for fabricating a quasi-SOI source/drain field effect transistor device, which comprises the steps of forming an active region of the device; forming a gate stack structure of the device; doping a source/drain extension region, and forming a first layer of side wall at two sides of the gate stack structure; forming a recessed source/drain structure; forming a quasi-SOI source/drain isolation layer; in-situ doping an epitaxial second semiconductor material source/drain, and activating by annealing; removing the previous dummy gate and re-depositing a high-k metal gate, if a post-gate process is employed; and forming contacts and metal interconnections.

Abstract: A method for fabricating a multi-gate structure device with a source and a drain having a quasi-SOI structure, comprising forming an active region in a shape of a fin bar, forming an oxide isolation layer for shallow trench isolation (STI), forming a polysilicon dummy gate, forming source and drain extension regions, forming the source and the drain with the quasi-SOI structure, and forming a high-K metal gate. Solution(s) consistent with the present innovations may be achieved by using a process method compatible with the conventional bulk silicon CMOS processes and can be easily integrated into the process flow. Moreover, innovations here may provide a small leakage current even in a case of having a short channel length, thereby reducing the power consumption of the device.

Abstract: Disclosed herein is a method for fabricating a FinFET with separated double gates on a bulk silicon, comprising: forming a pattern for a source, a drain and a thin bar connecting the source and the drain; forming an oxidation isolation layer; forming a gate structure and a source/drain structure; and forming a metal contact and a metal interconnection. By means of the method herein, it is very easy to fabricate the FinFET with separated double gates on the bulk silicon wafer, and the overall process flow is completely compatible with the conventional silicon-based very large scale integrated circuit manufacturing technology. Thus, the method herein is simple, convenient and has a short process period, greatly economizing the cost of the silicon wafer. In addition, by employing the FinFET with separated double gates fabricated by the method according to the invention, the short channel effect can be effectively suppressed.

Abstract: The present invention discloses a hexagonal programmable array based on a silicon nanowire field effect transistor and a method for fabricating the same. The array includes a nanowire device, a nanowire device connection region and a gate connection region, wherein, the nanowire device has a cylinder shape, and includes a silicon nanowire channel, a gate dielectric layer, and a gate region, the nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate region; the nanowire devices are arranged in a hexagon shape to form programming unit, the nanowire device connection region is a connection node of three nanowire devices and secured to a silicon supporter. The present invention can achieve a complex control logic of interconnections and is suitable for a digital/analog and a mixed-signal circuit having a high integration degree and a high speed.

Abstract: The present invention discloses a method of adjusting a threshold voltage of a multi-gate structure device, wherein, preparing the multi-gate structure device to be formed to have a channel impurity distribution with high doping on surface and lowly doping inside, where while a threshold voltage is adjusted by using impurity doping, the influences of the Coulomb impurity scattering on the carriers is reduced as much as possible, so that the mobility of the carriers is maintained at a higher level. Firstly, the present solution is able to make a multi-gate device obtain a larger range of a multi-threshold voltage; it is convenient for the various demands of the device in the circuit designing by IC designers.

Abstract: The present invention provides a method for fabricating a FinFET on a germanium or group III-V semiconductor substrate. The process flow of the method mainly includes: forming a pattern structure for a source, a drain and a fine bar connecting the source and the drain; forming an oxide isolation layer; forming a gate structure, a source and a drain structure; and forming metal contacts and metal interconnections. The method may allow an easy fabrication of a FinFET on a germanium or group III-V semiconductor substrate, and the entire process flow is similar to a conventional silicon-based integrated circuit fabrication technology despite it is achieved based on the germanium or group III-V semiconductor material. The fabrication process is simple, convenient and has a short period. In addition, the FinFET fabricated by the above process flow has a minimum width that can be controlled to about 20 nm.

Abstract: Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching.

Abstract: Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The present invention is especially suitable for testing a device with an ultra-small area (the effective channel area is less than 0.05 square microns). The present method can obtain trap distribution scenarios of the gate dielectric layer in the case of different materials and different processes.

Abstract: Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.

Abstract: A method for testing trap density in a gate dielectric layer of a semiconductor device having no substrate contact is provided in the invention. A source and a drain of the device are bilateral symmetric, and probes and cables of a test instrument connecting to the source and the drain are bilateral symmetric. Firstly, bias settings at the gate, the source and the drain are controlled so that the device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges.