Patents by Inventor Jieying KONG
Jieying KONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250112138Abstract: Microelectronic integrated circuit package structures include an apparatus having a substrate comprising a layer of glass, the substrate comprising one or more through glass vias (TGVs) extending through the layer of glass. Individual TGVs comprise a TGV sidewall, an organic dielectric layer on the TGV sidewall and a conductive layer on the organic dielectric layer.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Srinivas Pietambaram, Gang Duan, Sameer Paital, Zhixin Xie, Rahul Manepalli, Jieying Kong
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Publication number: 20250112136Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
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Publication number: 20250112140Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a core with a first width, and the core comprises a glass layer. In an embodiment, a via is provided through a thickness of the core, where the via is electrically conductive. In an embodiment, a first layer is provided over the core, where the first layer comprises a second width that is smaller than the first width. In an embodiment, a second layer is provided under the core, where the second layer comprises a third width that is smaller than the first width.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Inventors: Rahul BHURE, Mitchell PAGE, Joseph PEOPLES, Jieying KONG, Nicholas S. HAEHN, Astitva TRIPATHI, Bainye Francoise ANGOUA, Yosef KORNBLUTH, Daniel ROSALES-YEOMANS, Joshua STACEY, Aaditya Anand CANDADAI, Yonggang Yong LI, Tchefor NDUKUM, Scott COATNEY, Gang DUAN, Jesse JONES, Srinivas Venkata Ramanuja PIETAMBARAM, Dilan SENEVIRATNE, Matthew ANDERSON
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Publication number: 20250112163Abstract: An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged nanoparticles.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Pratyush Mishra, Pratyasha Mohapatra, Srinivas Pietambaram, Whitney Bryks, Mahdi Mohammadighaleni, Joshua Stacey, Travis Palmer, Yosef Kornbluth, Kuang Liu, Astitva Tripathi, Yuqin Li, Rengarajan Shanmugam, Xing Sun, Brian Balch, Darko Grujicic, Jieying Kong, Nicholas Haehn, Jacob Vehonsky, Mitchell Page, Vincent Obiozo Eze, Daniel Wandera, Sameer Paital, Gang Duan
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Patent number: 12191240Abstract: Embodiments disclosed herein include hybrid cores for electronic packaging applications. In an embodiment, a package substrate comprises a plurality of glass layers and a plurality of dielectric layers. In an embodiment, the glass layers alternate with the dielectric layers. In an embodiment, a through-hole through the plurality of glass layers and the plurality of dielectric layers is provided. In an embodiment a conductive through-hole via is disposed in the through-hole.Type: GrantFiled: August 13, 2019Date of Patent: January 7, 2025Assignee: Intel CorporationInventors: Jieying Kong, Srinivas Pietambaram, Gang Duan
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Publication number: 20250006623Abstract: Microelectronic integrated circuit package structures include one or more integrated circuit (IC) package metallization levels comprising metallization features. A dielectric material is adjacent to one or more of the metallization features, where the dielectric material comprises a matrix material and a surfactant. A plurality of substantially spherical pores are within the matrix material, where the substantially spherical pores are surrounded by an outer shell comprising the matrix material.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Applicant: Intel CorporationInventors: Shuqi Lai, Jieying Kong, Dilan Seneviratne, Whitney Bryks
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Patent number: 12125777Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first buildup layer and a second buildup layer over the first buildup layer. In an embodiment, a void is disposed through the second buildup layer. In an embodiment the electronic package further comprises a first pad over the second buildup layer. In an embodiment, the first pad covers the void.Type: GrantFiled: October 28, 2019Date of Patent: October 22, 2024Assignee: Intel CorporationInventors: Zhiguo Qian, Gang Duan, Kemal Aygün, Jieying Kong, Brandon C. Marin
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Patent number: 12033930Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.Type: GrantFiled: September 25, 2020Date of Patent: July 9, 2024Assignee: Intel CorporationInventors: Jieying Kong, Yiyang Zhou, Suddhasattwa Nad, Jeremy Ecton, Hongxia Feng, Tarek Ibrahim, Brandon Marin, Zhiguo Qian, Sarah Blythe, Bohan Shan, Jason Steill, Sri Chaitra Jyotsna Chavali, Leonel Arana, Dingying Xu, Marcel Wall
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Publication number: 20240222089Abstract: This disclosure describes designs and methods for via cleaning, peeling protective film, and providing mild surface roughening and cleaning of a computer chip. A system may include a first electrode configured to generate plasma associated with cleaning vias by etching a residual material associated with smearing; an electrostatic stage configured to generate an electrostatic force associated with peeling the dielectric protective film from the semiconductor; and a stage on which the semiconductor is positioned while the electrostatic stage peels the dielectric protective film from the semiconductor, wherein the plasma is further associated with roughening a surface of the semiconductor after peeling the dielectric protective film from the semiconductor.Type: ApplicationFiled: December 28, 2022Publication date: July 4, 2024Inventors: Ala OMER, Peumie ABEYRATNE KURAGAMA, Jieying KONG, Wendy LIN, Ao WANG
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Publication number: 20240217216Abstract: Embodiments disclosed herein include package substrates with glass stiffeners. In an embodiment, the package substrate comprises a first layer, where the first layer comprises glass. In an embodiment, the package substrate comprises a second layer over the first layer, where the second layer is a buildup film. In an embodiment, the package substrate further comprises an electrically conductive interconnect structure through the first layer and the second layer.Type: ApplicationFiled: December 29, 2022Publication date: July 4, 2024Inventors: Kristof DARMAWIKARTA, Tarek A. IBRAHIM, Srinivas V. PIETAMBARAM, Dilan SENEVIRATNE, Jieying KONG, Thomas HEATON, Whitney BRYKS, Vinith BEJUGAM, Junxin WANG, Gang DUAN
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Publication number: 20240112999Abstract: An electronic system comprising can have a substrate with a core layer formed from at least one layer of glass. The glass layers can each be stacked with a dielectric material disposed between each layer of glass. The glass layers can be prepatterned before assembly of the layered glass core system.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Inventors: Jieying Kong, Houssam Jomaa, Dilan Seneviratne, Whitney Bryks, Srinivas Venkata Ramanuja Pietambaram, Kristof Darmawikarta
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Publication number: 20240096561Abstract: An apparatus, system, and method for in-situ three-dimensional (3D) thin-film capacitor (TFC) are provided. A 3D TFC can include a glass core, a through glass via (TGV) in the glass core including first conductive material, the first conductive material forming a first electrode of the 3D MIM capacitor, a second conductive material acting as a second electrode of the 3D MIM capacitor, and a dielectric material in contact with the first and second conductive materials, the dielectric material extending vertically and horizontally and physically separating the first and second conductive materials.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Inventors: Mahdi Mohammadighaleni, Benjamin Duong, Shayan Kaviani, Joshua Stacey, Miranda Ngan, Dilan Seneviratne, Thomas Heaton, Srinivas Venkata Ramanuja Pietambaram, Whitney Bryks, Jieying Kong
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Publication number: 20240006285Abstract: Substrate assemblies having adhesion promotor layers and related methods are disclosed. An example apparatus includes a substrate, a dielectric layer, a first copper layer between the substrate and the dielectric layer, and a film between the dielectric layer and the first copper layer. The film including silicon and nitrogen and being substantially free of hydrogen. A via in the dielectric layer is to provide access to the first copper layer. A portion of the first copper layer uncovered in the via, a wall of the via and the portion of the first copper layer to be substantially free of fluorine. A seed copper layer positioned on the dielectric layer. The via wall and the portion of the first copper layer. The seed copper layer and the first copper layer define an undercut at an interface between the seed copper layer and the first copper layer.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Yi Yang, Suddhasattwa Nad, Xiaoying Guo, Jieying Kong, Ala Omer, Christy Sennavongsa, Wei Wei, Ao Wang
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Publication number: 20240006296Abstract: Microelectronic integrated circuit package structures include a first layer over a substrate, the first layer having a matrix material and a filler material within the matrix material. A second layer is on the first layer, the second layer comprising the matrix material or a second material, where the filler material is substantially absent from the second layer. A first portion of a conductive feature is on the second layer and a second portion of the conductive feature is on a sidewall of the first layer.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Jieying Kong, Peumie Abeyratne Kuragama, Ala Omer, Ao Wang, Dilan Seneviratne
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Publication number: 20230420353Abstract: An electronic device package comprises a substrate with a first side and a second side opposite the first side; a first conductive feature on the first side and having a first surface; a first dielectric material in contact with the first surface, wherein the first dielectric material has a first composition comprising silicon and nitrogen; a second conductive feature on the second side of the substrate and having a second surface; and a second dielectric material in contact with the second surface, wherein the second dielectric material has a second composition different than the first composition, and wherein a surface roughness of the second surface is greater than a surface roughness of the first surface.Type: ApplicationFiled: June 23, 2022Publication date: December 28, 2023Applicant: Intel CorporationInventors: Suddhasattwa Nad, Yi Yang, Jason Steill, Jieying Kong
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Publication number: 20230420348Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer is a dielectric material, and a trace on the first layer. In an embodiment, a pad is on the first layer, and a liner is over the first layer, the trace, and the pad, where a hole is provided through the liner. In an embodiment, the electronic package further comprises a second layer over the first layer, the trace, the pad, and the liner.Type: ApplicationFiled: June 28, 2022Publication date: December 28, 2023Inventors: Jieying KONG, Whitney BRYKS, Dilan SENEVIRATNE, Suddhasattwa NAD, Srinivas V. PIETAMBARAM
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Publication number: 20230405976Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.Type: ApplicationFiled: August 31, 2023Publication date: December 21, 2023Inventors: Jieying KONG, Gang DUAN, Srinivas PIETAMBARAM, Patrick QUACH, Dilan SENEVIRATNE
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Patent number: 11780210Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.Type: GrantFiled: September 18, 2019Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Jieying Kong, Gang Duan, Srinivas Pietambaram, Patrick Quach, Dilan Seneviratne
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Publication number: 20230207503Abstract: A system includes a metallic contact integrated onto a semiconductor integrated circuit substrate. The metallic contact has a contact surface to make electrical contact with a trace through a dielectric layer over the semiconductor circuit substrate and the metallic contact. The semiconductor circuit can include a trace that connects the contact to a package pad to enable external access to the signal from off the semiconductor circuit. The metallic contact includes a vertical lip extending vertically into the dielectric layer above the contact surface.Type: ApplicationFiled: December 24, 2021Publication date: June 29, 2023Inventors: Jieying KONG, Bainye Francoise ANGOUA, Dilan SENEVIRATNE, Whitney M. BRYKS, Jeremy D. ECTON
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Publication number: 20230098501Abstract: A system includes a metallic contact integrated onto a semiconductor integrated circuit substrate with a stress buffer dielectric between the contact and the bulk dielectric. The bulk dielectric typically covers an integrated circuit metal layer to provide electrical isolation of the circuitry. The semiconductor circuit can include a trace that connects the contact to a package pad to enable external access to the signal from off the semiconductor circuit. The stress buffer dielectric has higher elongation and lower filler loading relative to the bulk dielectric, which makes the stress buffer more pliable. The stress buffer is disposed between the contact and the bulk dielectric to improve stress response, reducing the possibility of delamination of the contact from the bulk dielectric.Type: ApplicationFiled: September 25, 2021Publication date: March 30, 2023Inventors: Sarah BLYTHE, Jieying KONG, Peumie ABEYRATNE KURAGAMA, Hongxia FENG
