Patents by Inventor Jie-Yu WANG

Jie-Yu WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240115097
    Abstract: A method of operating a cleaning system is provided herein. The method includes receiving a first battery pack including a first battery controller, receiving a first signal from the first battery controller, outputting, in response to receiving the first signal, a first control signal, operating a motor at a first predetermined constant power based on the first control signal, receiving a second battery pack including a second battery controller, receiving a second signal from the second battery controller, outputting, in response to receiving the second signal, a second control signal, and operating the motor at a second predetermined constant power based on the second control signal.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 11, 2024
    Inventors: Hei Man LEE, Jie YU, Li Feng WANG
  • Patent number: 11929418
    Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: March 12, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
  • Patent number: 11009967
    Abstract: A method for scanning a keyboard circuit is provided. The keyboard circuit includes a keyboard array, output wires, input wires, and a scanning circuit. Each of the output wires is electrically coupled to a corresponding column of key units of the keyboard array, respectively. Each of the input wires is electrically coupled to a corresponding row of key units of the keyboard array, and is provided with a pull-up resistor. The method includes: turning on and connecting open-drain transistors to the ground in a scanning interval to clean charges on the output wires; turning on the open-drain transistors and connecting the open-drain transistors to the ground sequentially in a scanning duration; and receiving detected electrical levels through the input wires, and when one of the detected electrical levels is substantially equal to the electrical level of the ground, determining that the corresponding key unit is pressed.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 18, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shi-Wei Zheng, Zuo-Hui Peng, Li Tong, Zhao-Ming Li, Jie-Yu Wang
  • Publication number: 20210096658
    Abstract: A method for scanning a keyboard circuit is provided. The keyboard circuit includes a keyboard array, output wires, input wires, and a scanning circuit. Each of the output wires is electrically coupled to a corresponding column of key units of the keyboard array, respectively. Each of the input wires is electrically coupled to a corresponding row of key units of the keyboard array, and is provided with a pull-up resistor. The method includes: turning on and connecting open-drain transistors to the ground in a scanning interval to clean charges on the output wires; turning on the open-drain transistors and connecting the open-drain transistors to the ground sequentially in a scanning duration; and receiving detected electrical levels through the input wires, and when one of the detected electrical levels is substantially equal to the electrical level of the ground, determining that the corresponding key unit is pressed.
    Type: Application
    Filed: September 25, 2020
    Publication date: April 1, 2021
    Inventors: Shi-Wei ZHENG, Zuo-Hui PENG, Li Tong, Zhao-Ming Li, Jie-Yu WANG