Abstract: In a general aspect, a high-voltage metal-oxide-semiconductor (HVMOS) device can include comprising a first gate dielectric layer disposed on a channel region of the HVMOS device and a second gate dielectric layer disposed on at least a portion of a drift region of the HVMOS device. The drift region can be disposed laterally adjacent to the channel region. The second gate dielectric layer can have a thickness that is greater than a thickness of the first gate dielectric layer.

Abstract: In a general aspect, a high-voltage metal-oxide-semiconductor (HVMOS) device can include comprising a first gate dielectric layer disposed on a channel region of the HVMOS device and a second gate dielectric layer disposed on at least a portion of a drift region of the HVMOS device. The drift region can be disposed laterally adjacent to the channel region. The second gate dielectric layer can have a thickness that is greater than a thickness of the first gate dielectric layer.

Abstract: In one general aspect, an apparatus can include a plurality of trench metal-oxide-semiconductor field effect transistors (MOSFET) devices formed within an epitaxial layer of a substrate, and a gate-runner trench disposed around the plurality of trench MOSFET devices and disposed within the epitaxial layer. The apparatus can also include a floating-field implant defined by a well implant and disposed around the gate-runner trench.

Abstract: In one general aspect, an apparatus can include a plurality of trench metal-oxide-semiconductor field effect transistors (MOSFET) devices formed within an epitaxial layer of a substrate, and a gate-runner trench disposed around the plurality of trench MOSFET devices and disposed within the epitaxial layer. The apparatus can also include a floating-field implant defined by a well implant and disposed around the gate-runner trench.

Abstract: In one general aspect, an apparatus can include a substrate, a gate electrode, and a gate dielectric having at least a portion disposed between the gate electrode and the substrate. The apparatus can include a heavily doped drain region disposed within the substrate, and a lightly doped drain region within the substrate and in contact with the heavily doped drain region. The apparatus can also include a medium doped drain region disposed within the lightly doped drain region and having a dopant concentration between a dopant concentration of the heavily doped drain region and a dopant concentration of the lightly doped drain region.

Abstract: A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.

Abstract: A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.

Abstract: A semiconductor device can include a source region near a working top surface of a semiconductor region. The device can also include a gate located above the working top surface and located laterally between the source and a drain region. The source region and the gate can at least partially laterally overlap a body region near the working top surface. The source region can include a first portion having the first conductivity type, a second portion having a second conductivity type, and a third portion having the second conductivity type. The second portion can be located laterally between the first and third portions and can penetrate into the semiconductor region to a greater depth than the third portion but no more than the first portion. The lateral location of the third portion can be determined at least in part using the lateral location of the gate.

Abstract: A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.

Abstract: A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.

Abstract: A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.

Abstract: A power MOSFET 100 has a source metal 112 that contacts silicided source regions 114 through vias 160 etched in an insulating layer 200. The silicide layer 225 provides for a relatively small but highly conductive contact and thus reduces RDSON. The insulating material may be any suitable material including and not limited to one or a combination of materials such as BPSG, PSG, silicon dioxide and silicon nitride. The insulating layer is relatively thin and does not extend deeply into the gate trench.

Abstract: A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N? doped, P? doped, and P+ doped semiconductor layers, the P? and P+ doped layers having a combined thickness of about 5 ?m to about 12 ?m. Recombination centers comprising noble metal impurities are disposed substantially in the N? and P? doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N? doped epitaxial layer on an N+ doped substrate, forming a P? doped layer in the N? doped epitaxial layer, forming a P+ doped layer in the P? doped layer, and forming in the P? and N? doped layers recombination centers comprising noble metal impurities. The P+ and P?doped layers have a combined thickness of about 5 ?m to about 12 ?m.

Abstract: A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N? doped, P? doped, and P+ doped semiconductor layers, the P? and P+ doped layers having a combined thickness of about 5 ?m to about 12 ?m. Recombination centers comprising noble metal impurities are disposed substantially in the N? and P? doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N? doped epitaxial layer on an N+ doped substrate, forming a P? doped layer in the N? doped epitaxial layer, forming a P+ doped layer in the P? doped layer, and forming in the P? and N? doped layers recombination centers comprising noble metal impurities. The P+ and P? doped layers have a combined thickness of about 5 ?m to about 12 ?m.

Abstract: A power MOSFET 100 has a source metal 112 that contacts silicided source regions 114 through vias 160 etched in an insulating layer 200. The silicide layer 225 provides for a relatively small but highly conductive contact and thus reduces RDSON. The insulating material may be any suitable material including and not limited to one or a combination of materials such as BPSG, PSG, silicon dioxide and silicon nitride.

Abstract: A power MOSFET 100 has a source metal 112 that contacts silicided source regions 114 through vias 160 etched in an insulating layer 200. The silicide layer 225 provides for a relatively small but highly conductive contact and thus reduces RDSON. The insulating material may be any suitable material including and not limited to one or a combination of materials such as BPSG, PSG, silicon dioxide and silicon nitride. The insulating layer is relatively thin and does not extend deeply into the gate trench, thereby reducing capacitance.

Abstract: A trench MOS-gated device has an upper surface and includes a substrate having an upper layer of doped monocrystalline semiconductor material of a first conduction type. A gate trench in the upper layer has sidewalls and a floor lined with a first dielectric material and a centrally disposed core formed of a second dielectric material extending upwardly from the first dielectric material on the trench floor and having lateral and top surfaces. The remainder of the trench is substantially filled with a conductive material that encompasses and contacts the lateral and top surfaces of the core of second dielectric material. A doped well region of a second conduction type overlies a drain zone of the first conduction type in the upper layer, and a heavily doped source region of the first conduction type contiguous to the gate trench and a heavily doped body region of the second conduction type are disposed in the well region at the upper surface of the device.

Abstract: A power MOSFET 100 has a source metal 112 that contacts silicided source regions 114 through vias 160 etched in an insulating layer 200. The silicide layer 225 provides for a relatively small but highly conductive contact and thus reduces RDSON. The insulating material may be any suitable material including and not limited to one or a combination of materials such as BPSG, PSG, silicon dioxide and silicon nitride. The insulating layer is relatively thin and does not extend deeply into the gate trench, thereby reducing capacitance.

Abstract: A trench MOS-gated device has an upper surface and includes a substrate having an upper layer of doped monocrystalline semiconductor material of a first conduction type. A gate trench in the upper layer has sidewalls and a floor lined with a first dielectric material and a centrally disposed core formed of a second dielectric material extending upwardly from the first dielectric material on the trench floor and having lateral and top surfaces. The remainder of the trench is substantially filled with a conductive material that encompasses and contacts the lateral and top surfaces of the core of second dielectric material. A doped well region of a second conduction type overlies a drain zone of the first conduction type in the upper layer, and a heavily doped source region of the first conduction type contiguous to the gate trench and a heavily doped body region of the second conduction type are disposed in the well region at the upper surface of the device.

Abstract: In an improved process for controlling and improving minority carrier lifetime in a P-i-N diode, platinum is deposited on a surface of a silicon semiconductor substrate containing at least one PN junction. The substrate is heated to a temperature of about 800° C., and the platinum is diffused into the substrate as its temperature is increased at a rate of about 5° C./minute to a first selected temperature of about 850-950° C. Platinum diffusion is continued while the substrate is maintained at the first selected temperature for about 30-60 minutes. The substrate temperature is then increased at a rate of about 5° C./minute to a second selected temperature above 950° C. to about 1000° C., and the substrate is maintained at the second selected temperature for about 5-30 minutes before cooling.