Patents by Inventor Jignesh CHAUHAN

Jignesh CHAUHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240163725
    Abstract: A network device may select a first user plane function for establishing, with a user equipment, a protocol data unit session with a single flow and may receive an application function trigger associated with a first new flow for a first application of the user equipment. The network device may cause a first traffic filter to be provided to the user equipment to enable the user equipment to route first application traffic, based on the first traffic filter, to a second user plane function and a first multi-access edge computing device associated with the second user plane function.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Applicant: Verizon Patent and Licensing Inc.
    Inventors: Sudhakar Reddy PATIL, Jignesh S. PANCHAL, Maqbool CHAUHAN, Violeta CAKULEV, Vishwanath RAMAMURTHI
  • Publication number: 20200403629
    Abstract: A method and system to perform the verification of measures done by a sensor in quasi real-time. The sensor verification may be implemented at two different levels—a functionality level and a measurement level. At the functionality level, a consistency check of information from different variables may be processed at sensor level depending on the functionality of the physical system being measured. At the measurement level, diagnostics may be performed of the circuits present in the measurement path by specific circuitry and at suitable instants of time to guarantee a Fault Tolerant Time Interval while minimizing sample loss. This may be achieved, at least in part, by increasing the measuring sample rate.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Inventors: Antoni FERRE FABREGAS, David GAMEZ ALARI, Federico GIORDANO, Jignesh CHAUHAN, Om PRAKASH, Abhishek SHARMA
  • Patent number: 10790844
    Abstract: A method and system to perform the verification of measures done by a sensor in quasi real-time. The sensor verification may be implemented at two different levels—a functionality level and a measurement level. At the functionality level, a consistency check of information from different variables may be processed at sensor level depending on the functionality of the physical system being measured. At the measurement level, diagnostics may be performed of the circuits present in the measurement path by specific circuitry and at suitable instants of time to guarantee a Fault Tolerant Time Interval while minimizing sample loss. This may be achieved, at least in part, by increasing the measuring sample rate.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: September 29, 2020
    Assignee: Lear Corporation
    Inventors: Antoni Ferre Fabregas, David Gamez Alari, Federico Giordano, Jignesh Chauhan, Om Prakash, Abhishek Sharma
  • Publication number: 20190393884
    Abstract: A method and system to perform the verification of measures done by a sensor in quasi real-time. The sensor verification may be implemented at two different levels—a functionality level and a measurement level. At the functionality level, a consistency check of information from different variables may be processed at sensor level depending on the functionality of the physical system being measured. At the measurement level, diagnostics may be performed of the circuits present in the measurement path by specific circuitry and at suitable instants of time to guarantee a Fault Tolerant Time Interval while minimizing sample loss. This may be achieved, at least in part, by increasing the measuring sample rate.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Inventors: Antoni FERRE FABREGAS, David GAMEZ ALARI, Federico GIORDANO, Jignesh CHAUHAN, Om PRAKASH, Abhishek SHARMA
  • Publication number: 20170010896
    Abstract: A method of updating a bootloader includes a slave controller that includes a central processing unit in communication with non-volatile memory having a shared memory architecture. The shared memory architecture including a non-volatile application memory block having application code and a non-volatile launcher memory block having bootloader code for initiating the slave controller. The method including a step of storing updated code to an application memory block of the non-volatile memory. The updated code includes a first code section having application code for application functions, a second code section having updated bootupdater code, and a third code section having image code for an updated bootloader. Slave controller receives indication to update the bootloader code stored in the non-volatile launcher memory block and then executes the bootupdater stored in the application memory block to update the bootloader stored in the launcher memory block from the image code for an updated bootloader.
    Type: Application
    Filed: July 6, 2015
    Publication date: January 12, 2017
    Inventors: David Gamez ALARI, Jordi Moreno AYMAMI, Antoni Ferré FÀBREGAS, Jignesh CHAUHAN, Rahul RANADE