Patents by Inventor Jignesh Trivedi

Jignesh Trivedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Processor executing plural instruction sets (ISA's) with ability to have plural ISA's in different pipeline stages at same time
    Patent number: 6430674
    Abstract: A method and apparatus for transitioning a processor from a first mode of operation for processing a first instruction set architecture (instruction set) to a second mode of operation for processing a second set instruction set. The method provides that instructions of a first instruction set architecture (instruction set) are processed in a pipelined processor in a first mode of operation, and instructions of a second, different, instruction set, are processed in the pipelined processor in a second, different, mode of operation. While operating in one mode and before a switch to the other mode occurs, the pipeline is loaded with a set of instructions that transition the processor from one mode to the other, wherein the set of instructions are substantially insensitive to the mode that the processor operates in.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: August 6, 2002
    Assignee: Intel Corporation
    Inventors: Jignesh Trivedi, Tse-Yu Yeh