Patents by Inventor Jih-Chang Lien
Jih-Chang Lien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7005698Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.Type: GrantFiled: September 23, 2003Date of Patent: February 28, 2006Assignee: Nanya Technology CorporationInventors: Chi-Hui Lin, Jeng-Ping Lin, Pei-Ing Lee, Jih-Chang Lien
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Patent number: 6734066Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.Type: GrantFiled: December 2, 2002Date of Patent: May 11, 2004Assignee: Nanya Technology CorporationInventors: Chi-Hui Lin, Jeng-Ping Lin, Pei-Ing Lee, Jih-Chang Lien
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Publication number: 20040057328Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive stud, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive stud is disposed in the lower trench of the substrate. The source region is formed in the substrate adjacent to the upper conductive stud having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate of the outside conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate of the outside first conductive layer.Type: ApplicationFiled: September 23, 2003Publication date: March 25, 2004Applicant: Nanya Technology CorporationInventors: Chi-Hui Lin, Jeng-Ping Lin, Pei-Ing Lee, Jih-Chang Lien
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Publication number: 20030218208Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive stud, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive stud is disposed in the lower trench of the substrate. The source region is formed in the substrate adjacent to the upper conductive stud having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate of the outside conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate of the outside first conductive layer.Type: ApplicationFiled: December 2, 2002Publication date: November 27, 2003Applicant: Nanya Technology CorporationInventors: Chi-Hui Lin, Jeng-Ping Lin, Pei-Ing Lee, Jih-Chang Lien
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Patent number: 6521543Abstract: The present invention provides a multiple exposure method for defining a rectangular pattern on a photoresist layer. The method comprises the following steps. First, a rectangular region is defined on the photoresist layer, having a first margin pair and a second margin pair corresponding to the rectangular pattern. Next, a first exposure process is performed on a first exposure region of the photoresist layer. An extension of the first margin pair acts as a boundary between the first exposure region and the rectangular region. Next, a second exposure process is performed on a second exposure region of the photoresist layer. An extension of the second margin pair acts as a boundary between the second exposure region and the rectangular region. Finally, a development process is performed on the first exposure region and the second exposure region to create the rectangular pattern on a substrate.Type: GrantFiled: August 17, 2001Date of Patent: February 18, 2003Assignee: Nanya Technology CorporationInventor: Jih-Chang Lien
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Publication number: 20020127889Abstract: The present invention provides a multiple exposure method for defining a rectangular pattern on a photoresist layer. The method comprises the following steps. First, a rectangular region is defined on the photoresist layer, having a first margin pair and a second margin pair corresponding to the rectangular pattern. Next, a first exposure process is performed on a first exposure region of the photoresist layer. An extension of the first margin pair acts as a boundary between the first exposure region and the rectangular region. Next, a second exposure process is performed on a second exposure region of the photoresist layer. An extension of the second margin pair acts as a boundary between the second exposure region and the rectangular region. Finally, a development process is performed on the first exposure region and the second exposure region to create the rectangular pattern on a substrate.Type: ApplicationFiled: August 17, 2001Publication date: September 12, 2002Applicant: NANYA TECHNOLOGY CORPORATIONInventor: Jih-Chang Lien
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Patent number: 5680345Abstract: A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of field oxide to form vertically walled cavities around the active regions. The tunnel oxide, floating gate, interpoly dielectric, and the control gate are formed within each cavity so that the floating gate overlaps the control gate along the vertical walls. As a result, capacitive coupling between the gates is maintained, yet the horizontal dimensions of the cell decrease. Similarly, the absence of birds' beaks facilitates higher cell density in the core.Type: GrantFiled: June 6, 1995Date of Patent: October 21, 1997Assignee: Advanced Micro Devices, Inc.Inventors: James Juen Hsu, Steven W. Longcor, Jih-Chang Lien
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Patent number: 5661055Abstract: A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of field oxide to form vertically walled cavities around the active regions. The tunnel oxide, floating gate, interpoly dielectric, and the control gate are formed within each cavity so that the floating gate overlaps the control gate along the vertical walls. As a result, capacitive coupling between the gates is maintained, yet the horizontal dimensions of the cell decrease. Similarly, the absence of birds' beaks facilitates higher cell density in the core.Type: GrantFiled: June 7, 1995Date of Patent: August 26, 1997Assignee: Advanced Micro Devices, Inc.Inventors: James Juen Hsu, Steven W. Longcor, Jih-Chang Lien
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Patent number: 4987465Abstract: An ESD protection device for CMOS integrated circuit inputs is disclosed. Two clamp components, coupled by a current limiting device, couple the pad to the circuitry of the chip. The device prevents damage to the circuit from an ESD of approximately 8000 or more volts at an input terminal.Type: GrantFiled: October 28, 1988Date of Patent: January 22, 1991Assignee: Advanced Micro Devices, Inc.Inventors: Steven W. Longcor, Kuang-Yeh Chang, Jih-Chang Lien, David M. Rogers
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Patent number: 4635347Abstract: A method for constructing titanium silicide integrated circuit gate electrodes and interconnections is disclosed. The method finds particularly useful applications in metal-oxide semiconductor integrated circuit fabrication. Following standard active and passive circuit component construction, a thin film of titanium is overlayed on the die structure covering thereby the pre-patterned polysilicon gates and interconnections. The die is then rapidly heated and baked to form a silicide layer superposing said polysilicon. The undesired titanium layer over other areas can be stripped using simple ammonium hydroxide/hydrogen etching and cleaning solution. Titanium silicide electrodes and interconnections are self-aligned and have a sheet resistance of 1 to 5 ohms per square.Type: GrantFiled: March 29, 1985Date of Patent: January 13, 1987Assignee: Advanced Micro Devices, Inc.Inventors: Jih-Chang Lien, Hsingya A. Wang
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Patent number: 4514897Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.Type: GrantFiled: April 26, 1984Date of Patent: May 7, 1985Assignee: Texas Instruments IncorporatedInventors: Te-Long Chiu, Jih-Chang Lien
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Patent number: 4467453Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.Type: GrantFiled: February 28, 1983Date of Patent: August 21, 1984Assignee: Texas Instruments IncorporatedInventors: Te-Long Chiu, Jih-Chang Lien
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Patent number: 4408385Abstract: Resistor elements for MOS integrated circuits are made by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The resistor elements are in a part of a polycrystalline silicon layer which is also used as a gate for an MOS transistor and as an interconnection overlying field oxide. Resistors of this type are ideally suited for load devices in static RAM cells.Type: GrantFiled: June 23, 1980Date of Patent: October 11, 1983Assignee: Texas Instruments IncorporatedInventors: G. R. Mohan Rao, John S. Stanczak, Jih-chang Lien, Shyam Bhatia
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Patent number: 4376947Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.Type: GrantFiled: September 4, 1979Date of Patent: March 15, 1983Assignee: Texas Instruments IncorporatedInventors: Te-Long Chiu, Jih-Chang Lien
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Patent number: 4370798Abstract: Integrated circuit resistor elements ideally suited for load devices in static MOS RAM cells are made in second-level polycrystalline silicon by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The second-level polysilicon is insulated from first-level polysilicon by multi-layer insulation; first, a thermal oxide layer provides better edge breakdown characteristics for transistors, then secondly a layer of doped deposited oxide provides improved step coverage, and finally an undoped deposited oxide is used to prevent out diffusion from doped oxide to second level polysilicon which would change the characteristics of the resistors.Type: GrantFiled: July 20, 1981Date of Patent: February 1, 1983Assignee: Texas Instruments IncorporatedInventors: Jih-Chang Lien, Te-Long Chiu
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Patent number: 4291328Abstract: Integrated circuit resistor elements ideally suited for load devices in static MOS RAM cells are made in second-level polycrystalline silicon by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The second-level polysilicon is insulated from first-level polysilicon by multi-layer insulation; first, a thermal oxide layer provides better edge breakdown characteristics for transistors, then secondly a layer of doped deposited oxide provides improved step coverage, and finally an undoped deposited oxide is used to prevent out diffusion from doped oxide to second level polysilicon which would change the characteristics of the resistors.Type: GrantFiled: June 15, 1979Date of Patent: September 22, 1981Assignee: Texas Instruments IncorporatedInventors: Jih-Chang Lien, Te-Long Chiu
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Patent number: 4234889Abstract: A double-level polycrystalline silicon structure for an N-channel MOS integrated circuit is disclosed including a metal interconnect level. Contact between the metal interconnect level and N+ diffused moat areas is made through discrete second-level polysilicon areas which reduce the step from metal level to moat level, thus increasing yields. Also, connections from the metal level to the first level polysilicon are made using a discrete area of second level polysilicon to minimize the step.Type: GrantFiled: May 31, 1977Date of Patent: November 18, 1980Assignee: Texas Instruments IncorporatedInventors: Joseph H. Raymond, Jr., Jih-Chang Lien
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Patent number: 4208781Abstract: Resistor elements for MOS integrated circuits are made by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The resistor elements are in a part of a polycrystalline silicon layer which is also used as a gate for an MOS transistor and as an interconnection overlying field oxide. Resistors of this type are ideally suited for load devices in static RAM cells.Type: GrantFiled: June 15, 1978Date of Patent: June 24, 1980Assignee: Texas Instruments IncorporatedInventors: G. R. Mohan Rao, John S. Stanczak, Jih-Chang Lien, Shyam Bhatia
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Patent number: 4110776Abstract: Resistor elements for MOS integrated circuits are made by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The resistor elements are in a part of a polycrystalline silicon layer which is also used as a gate for an MOS transistor and as an interconnection overlying field oxide. Resistors of this type are ideally suited for load devices in static RAM cells.Type: GrantFiled: September 27, 1976Date of Patent: August 29, 1978Assignee: Texas Instruments IncorporatedInventors: G. R. Mohan Rao, John S. Stanczak, Jih-Chang Lien, Shyam Bhatia