Patents by Inventor Jih-Chao CHIU

Jih-Chao CHIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230395725
    Abstract: A method includes forming a fin over a substrate, the fin comprising alternately stacking first oxide-based semiconductor layers and second oxide-based semiconductor layers, removing the second oxide-based semiconductor layers to form a plurality of spaces each between corresponding ones of the first oxide-based semiconductor layers, and depositing in sequence a gate dielectric layer and a gate metal into the plurality of spaces each between corresponding ones of the second oxide-based semiconductor layers.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jih-Chao CHIU, Song-Ling LI, Chee-Wee LIU
  • Publication number: 20230397501
    Abstract: A method of forming a memory device including forming a bottom electrode via (BEVA) in a dielectric layer, forming a magnetic tunnel junction (MTJ) multilayer structure over the BEVA, forming a top electrode on the MTJ multilayer structure, patterning the MTJ multilayer structure using the top electrode as an etch mask to form a MTJ stack, forming a first interlayer dielectric (ILD) layer over the MTJ stack, and after forming the first ILD layer, forming a ferromagnetic metal that exerts a magnetic field on the MTJ stack.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Ya-Jui TSOU, Jih-Chao CHIU, Huan-Chi SHIH, Chee-Wee LIU, Shao-Yu LIN, Chih-Lin WANG
  • Publication number: 20230268355
    Abstract: A method for fabricating an integrated circuit device is provided. The method includes forming a field effect transistor (FET) on a semiconductor substrate; depositing a first dielectric layer over the FET; depositing a first metal-containing dielectric layer over the first dielectric layer; and forming a first thin film transistor (TFT) over the first metal-containing dielectric layer.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jih-Chao CHIU, Chee-Wee LIU
  • Publication number: 20230027792
    Abstract: A memory device includes a spin-orbit-transfer (SOT) bottom electrode, an SOT ferromagnetic free layer, a first tunnel barrier layer, a spin-transfer-torque (STT) ferromagnetic free layer, a second tunnel barrier layer and a reference layer. The SOT ferromagnetic free layer is over the SOT bottom electrode. The SOT ferromagnetic free layer has a magnetic orientation switchable by the SOT bottom electrode using a spin Hall effect or Rashba effect. The first tunnel barrier layer is over the SOT ferromagnetic free layer. The STT ferromagnetic free layer is over the first tunnel barrier layer and has a magnetic orientation switchable using an STT effect. The second tunnel barrier layer is over the STT ferromagnetic free layer. The second tunnel barrier layer has a thickness different from a thickness of the first tunnel barrier layer. The reference layer is over the second tunnel barrier layer and has a fixed magnetic orientation.
    Type: Application
    Filed: May 4, 2022
    Publication date: January 26, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jih-Chao CHIU, Ya-Jui TSOU, Wei-Jen CHEN, Chee-Wee LIU, Shao-Yu LIN, Chih-Lin WANG