Patents by Inventor Jih-Chen Wang

Jih-Chen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9472247
    Abstract: A memory includes a first memory cell, a second memory cell, a latch unit, and a switch unit. The latch unit has a true node and a complement node. The switch unit is responsive to a first control signal and a second control signal, and is configured to connect the first memory cell to the true node and to disconnect the second memory cell from the complement node in response to the first control signal and to connect the second memory cell to the complement node and to disconnect the first memory cell from the true node in response to the second control signal. A semiconductor device that includes the memory is also disclosed. A method for testing the memory is also disclosed.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Hsiung Kuo, Gu-Huan Li, Jih-Chen Wang, Chung-Chieh Chen
  • Publication number: 20160240233
    Abstract: A memory includes a first memory cell, a second memory cell, a latch unit, and a switch unit. The latch unit has a true node and a complement node. The switch unit is responsive to a first control signal and a second control signal, and is configured to connect the first memory cell to the true node and to disconnect the second memory cell from the complement node in response to the first control signal and to connect the second memory cell to the complement node and to disconnect the first memory cell from the true node in response to the second control signal. A semiconductor device that includes the memory is also disclosed. A method for testing the memory is also disclosed.
    Type: Application
    Filed: February 13, 2015
    Publication date: August 18, 2016
    Inventors: CHENG-HSIUNG KUO, GU-HUAN LI, JIH-CHEN WANG, CHUNG-CHIEH CHEN
  • Patent number: 9418713
    Abstract: A sense amplifier includes four sub-circuits: pre-charge, sense enable, sense output, and buffer. The pre-charge sub-circuit provides a voltage between zero volts and the positive power supply (denoted VDD) to the sense enable sub-circuit. The sense enable sub-circuit is configured to adjust the received voltage based on the sensed value of bit lines and sends the adjusted voltage to the sense output sub-circuit. The sense output sub-circuit removes interference, inverts and amplifies the adjusted voltage, and sends an output voltage to the buffer sub-circuit. The buffer sub-circuit amplifies the output voltage of the sense output sub-circuit and provides it to an output bus.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Caleb Yu-Sheng Cho, Jih-Chen Wang, Yu-Fan Lin
  • Publication number: 20150262629
    Abstract: A sense amplifier includes four sub-circuits: pre-charge, sense enable, sense output, and buffer. The pre-charge sub-circuit provides a voltage between zero volts and the positive power supply (denoted VDD) to the sense enable sub-circuit. The sense enable sub-circuit is configured to adjust the received voltage based on the sensed value of bit lines and sends the adjusted voltage to the sense output sub-circuit. The sense output sub-circuit removes interference, inverts and amplifies the adjusted voltage, and sends an output voltage to the buffer sub-circuit. The buffer sub-circuit amplifies the output voltage of the sense output sub-circuit and provides it to an output bus.
    Type: Application
    Filed: May 28, 2015
    Publication date: September 17, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Caleb Yu-Sheng CHO, Jih-Chen WANG, Yu-Fan LIN
  • Patent number: 9070422
    Abstract: A sense amplifier includes four sub-circuits: pre-charge, sense enable, sense output, and buffer. The pre-charge sub-circuit provides a voltage between zero volts and the positive power supply (denoted VDD) to the sense enable sub-circuit. The sense enable sub-circuit is configured to adjust the received voltage based on the sensed value of bit lines and sends the adjusted voltage to the sense output sub-circuit. The sense output sub-circuit removes interference, inverts and amplifies the adjusted voltage, and sends an output voltage to the buffer sub-circuit. The buffer sub-circuit amplifies the output voltage of the sense output sub-circuit and provides it to an output bus.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: June 30, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Caleb Yu-Sheng Cho, Jih-Chen Wang, Yu-Fan Lin
  • Publication number: 20140185400
    Abstract: A sense amplifier includes four sub-circuits: pre-charge, sense enable, sense output, and buffer. The pre-charge sub-circuit provides a voltage between zero volts and the positive power supply (denoted VDD) to the sense enable sub-circuit. The sense enable sub-circuit is configured to adjust the received voltage based on the sensed value of bit lines and sends the adjusted voltage to the sense output sub-circuit. The sense output sub-circuit removes interference, inverts and amplifies the adjusted voltage, and sends an output voltage to the buffer sub-circuit. The buffer sub-circuit amplifies the output voltage of the sense output sub-circuit and provides it to an output bus.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Caleb Yu-Sheng CHO, Jih-Chen WANG, Yu-Fan LIN
  • Patent number: 7683698
    Abstract: A charge pump circuit is provided which includes at least two charge pump stages connected in series with a front charge pump stage having a first transistor for receiving an input voltage and a last charge pump stage having a second transistor for providing an output voltage. The first transistor is configured to operate at a first threshold voltage and the second transistor is configured to operate at a second threshold voltage different than the first threshold voltage.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: March 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ting Chu, Yong-Shiuan Tsair, Kuo-Wei Chu, Cheng-Hsiung Kuo, Jih-Chen Wang
  • Publication number: 20090051413
    Abstract: A charge pump circuit is provided which includes at least two charge pump stages connected in series with a front charge pump stage having a first transistor for receiving an input voltage and a last charge pump stage having a second transistor for providing an output voltage. The first transistor is configured to operate at a first threshold voltage and the second transistor is configured to operate at a second threshold voltage different than the first threshold voltage.
    Type: Application
    Filed: August 20, 2007
    Publication date: February 26, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Ting Chu, Yong-Shiuan Tsair, Kuo-Wei Chu, Cheng-Hsiung Kuo, Jih-Chen Wang