Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a fin disposed over a semiconductor substrate, and the fin has a first width. The structure further includes an isolation region disposed around the fin, a gate electrode disposed over the fin and the isolation region, and a fill material disposed in the gate electrode. The fill material is in contact with a top surface of a portion of the semiconductor substrate, the top surface has at least a portion having a substantially flat cross-section, and the portion of the top surface has a second width substantially greater than the first width.

Abstract: A semiconductor device includes a substrate; a first fin structure extending along a first lateral direction; a second fin structure extending along the first lateral direction; a first gate structure extending along a second lateral direction and straddles the first fin structure; a second gate structure extending along the second lateral direction and straddles the second fin structure. The semiconductor device further includes a dielectric cut structure that separates the first and second gate structures from each other. The dielectric cut structure extends into the substrate and comprises a first portion and a second portion. A width of the first portion along the second lateral direction increases with increasing depth into the substrate and a width of the second portion along the second lateral direction decreases with increasing depth into the substrate. The second portion is located below the first portion.

Abstract: A method of forming a FinFET device includes following steps. A substrate is provided with a plurality of fins thereon, an isolation layer thereon covering lower portions of the fins, a plurality of dummy strips across the fins, and a dielectric layer aside the dummy strips. The dummy strips is cut to form a trench in the dielectric layer. A first insulating structure is formed in the trench, wherein first and second groups of the dummy strips are beside the first insulating structure. A dummy strip is removed from the first group of the dummy strips to form a first opening that exposes portions of the fins under the dummy strip. The portions of the fins are removed to form a plurality of second openings below the first opening, wherein each second opening has a middle-wide profile. A second insulating structure is formed in the first and second openings.

Abstract: A method of forming a FinFET device includes following steps. A substrate is provided with a plurality of fins thereon, an isolation layer thereon covering lower portions of the fins, a plurality of dummy strips across the fins, and a dielectric layer aside the dummy strips. The dummy strips is cut to form a trench in the dielectric layer. A first insulating structure is formed in the trench, wherein first and second groups of the dummy strips are beside the first insulating structure. A dummy strip is removed from the first group of the dummy strips to form a first opening that exposes portions of the fins under the dummy strip. The portions of the fins are removed to form a plurality of second openings below the first opening, wherein each second opening has a middle-wide profile. A second insulating structure is formed in the first and second openings.

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes first fins, second fins, a first gate strip, a second gate strip and a comb-like insulating structure. The first and second fins are disposed on a substrate. The first gate strip is disposed across the first fins. The second gate strip is disposed across the second fins. The comb-like insulating structure is disposed between the first gate strip and the second gate strip and has a plurality of comb tooth parts. In some embodiments, each of the comb tooth parts has a middle-wide profile.

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes first fins, second fins, a first gate strip, a second gate strip and a comb-like insulating structure. The first and second fins are disposed on a substrate. The first gate strip is disposed across the first fins. The second gate strip is disposed across the second fins. The comb-like insulating structure is disposed between the first gate strip and the second gate strip and has a plurality of comb tooth parts. In some embodiments, each of the comb tooth parts has a middle-wide profile.

Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.

Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.

Abstract: Semiconductor devices and methods of manufacture are disclosed. A representative transistor device includes two fins over a workpiece. An insulating material is over the fins. The insulating material is not disposed between the fins. A dielectric material is over sidewalls of the insulating material and over a portion of the workpiece between the fins. A gate is over the dielectric material. The gate includes a first conductive material and a second conductive material over the first conductive material. The second conductive material is recessed below a top surface of the insulating material. The second conductive material has a top surface with a rounded profile.

Abstract: Semiconductor devices and methods of manufacture are disclosed. A representative transistor device includes two fins over a workpiece. An insulating material is over the fins. The insulating material is not disposed between the fins. A dielectric material is over sidewalls of the insulating material and over a portion of the workpiece between the fins. A gate is over the dielectric material. The gate includes a first conductive material and a second conductive material over the first conductive material. The second conductive material is recessed below a top surface of the insulating material. The second conductive material has a top surface with a rounded profile.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including a gate dielectric and a gate disposed over the gate dielectric, and reshaping a top surface of the gate to form a gate with a rounded profile.

Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including a gate dielectric and a gate disposed over the gate dielectric, and reshaping a top surface of the gate to form a gate with a rounded profile.

Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.

Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.

Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.

Abstract: Disclosed is a seasoning method for an etch chamber for improving the passing rate, comprising the steps of: introducing a wafer or plural control wafers into the etch chamber; introducing reacting gases into the etch chamber; applying power to top and bottom electrodes of the etch chamber to plasmarize the reacting gases; and adjusting the gate valve of the etch chamber to 90 to 100% of the fully open position, thereby reducing the amount of by-products and eliminating the factors for reducing the passing rate. The seasoning method of this invention is based on a low pressure, high flow-rate sluicing mechanism, where the atmospheric flow and high vacuuming ability would remove the maximum amount of polymer particles and flaking from the etch chamber.