Abstract: The present invention discloses an IC test method including the following steps: generating N test patterns; testing each of M chip(s) according to the N test patterns so as to generate N×M records of quiescent DC current (IDDQ) data; generating N reference values according to the N×M records, in which each of the N reference values is generated according to M record(s) of the N×M records, and the M record(s) and the reference value generated thereupon are related to the same one of the N test patterns; obtaining a reference order of the N test patterns according to the N reference values and a sorting rule; reordering the N×M records by the reference order so as to obtain reordered N×M records; generating an IDDQ range according to the reordered N×M records; and determining whether any of the M chip(s) is defective based on the IDDQ range.

Abstract: An electronic device includes a controller, a user interface and a sensor. The user interface and the sensor are coupled to the controller. The user interface is configured to send a first user command to the controller to control the controller to enter a burst mode. The controller is configured to control the sensor to continuously sense a chip or an environment where the chip is located to generate multiple sensing values, and to generate a sensing data according to the sensing values after the controller receives the first user command to enter the burst mode.

Abstract: A circuit debugging method includes: utilizing a debugging circuit to determine an operating status of a specific circuit to generate a result; utilizing a register located in a scan chain path to store the result, wherein the scan chain path is arranged for a scan test; and utilizing an output pad located in the scan chain path to output the result, wherein the result is arranged to be indicative of the operating status of the specific circuit.

Abstract: An electronic device includes a controller, a user interface and a sensor. The user interface and the sensor are coupled to the controller. The user interface is configured to send a first user command to the controller to control the controller to enter a burst mode. The controller is configured to control the sensor to continuously sense a chip or an environment where the chip is located to generate multiple sensing values, and to generate a sensing data according to the sensing values after the controller receives the first user command to enter the burst mode.

Abstract: The present invention discloses an IC test method including the following steps: generating N test patterns; testing each of M chip(s) according to the N test patterns so as to generate N×M records of quiescent DC current (IDDQ) data; generating N reference values according to the N×M records, in which each of the N reference values is generated according to M record(s) of the N×M records, and the M record(s) and the reference value generated thereupon are related to the same one of the N test patterns; obtaining a reference order of the N test patterns according to the N reference values and a sorting rule; reordering the N×M records by the reference order so as to obtain reordered N×M records; generating an IDDQ range according to the reordered N×M records; and determining whether any of the M chip(s) is defective based on the IDDQ range.

Abstract: A voltage and frequency scaling apparatus includes a processor, at least one sensor and a controller. The at least one sensor is electrically coupled to the processor. The at least one sensor measures at least one device characteristic of at least one logic circuit of a system on chip, and transmits at least one sensing result to the processor. The processor generates a control signal according to the at least one sensing result. The controller receives the control signal and adjusts at least one of the operating frequency and the operating voltage of at least one logic circuit. Furthermore, a system on chip (SoC) and a voltage and frequency scaling method are also described herein.

Abstract: A circuit debugging method includes: utilizing a debugging circuit to determine an operating status of a specific circuit to generate a result; utilizing a register located in a scan chain path to store the result, wherein the scan chain path is arranged for a scan test; and utilizing an output pad located in the scan chain path to output the result, wherein the result is arranged to be indicative of the operating status of the specific circuit.

Abstract: A method for deciding a scan clock domain allocation of an integrated circuit includes: utilizing a circuit netlist file and a timing constraints file of the integrated circuit to find out the amount of crossing paths between any two function clock domains of a plurality of function clock domains, and generate a clock domain report file; and grouping the plurality of function clock domains and allocating the plurality of function clock domains after being grouped into a plurality of scan clock domains according to the clock domain report file.

Abstract: A method for estimating a clock skew between a first clock and a second clock. The method includes the steps of detecting the clock skew to generate a detection resultant signal representing the clock skew; and determining time unit of a signal processing process, and estimating the clock skew according to the time unit of the signal processing process and the detection resultant signal.

Abstract: The present invention discloses a clock edge detection device capable of detecting the positive and negative edges of a target clock, comprising: a delay circuit for receiving the target clock and transmitting it; a register circuit coupled to the delay circuit for recording and outputting plural target clock levels in accordance with a working clock; a positive edge detection circuit including a plurality of positive edge detectors coupled to the register circuit for detecting the positive edge of the target clock; and a negative edge detection circuit including a plurality of negative edge detectors coupled to the register circuit for detecting the negative edge of the target clock, wherein the positive edge detection circuit is operable to perform a logic operation to the target clock levels while the negative edge detection circuit is operable to perform a different logic operation to the target clock levels.

Abstract: A PLL status detection circuit and its associated method are disclosed herein. The circuit and the method are used to detect a PLL clock generated by a PLL of a chip to determine a status of the PLL. The PLL status detection circuit includes a counter, a status analyzing circuit and a status storing circuit. The counter is configured to generate a count value by counting cycles of the PLL clock according to a control signal. The status analyzing circuit, which is coupled to the counter, is configured to analyze the count value according to the control signal to generate an analyzed result. The status storing circuit, which is coupled to the status analyzing circuit, is configured to store the analyzed result. The status storing circuit is coupled to a scan chain of the chip so that the analyzed result is transmitted via the scan chain.

Abstract: A test system, comprising: a BIST circuit for generating a first signal; a storage apparatus, for storing the first signal to generate a second signal; a first logic circuit, for generating a third signal; a second logic circuit; a register; and a passby circuit. In a first mode, the BIST circuit transmits the first signal to the storage device, the storage device outputs the second signal to the register for registering, and then the register outputs the registered second signal to the BIST circuit to test the storage apparatus. In a second mode, the first logic circuit transmits a third signal to the register for registering, and then the register outputs the registered third signal to the second logic circuit.

Abstract: The present invention discloses a clock edge detection device capable of detecting the positive and negative edges of a target clock, comprising: a delay circuit for receiving the target clock and transmitting it; a register circuit coupled to the delay circuit for recording and outputting plural target clock levels in accordance with a working clock; a positive edge detection circuit including a plurality of positive edge detectors coupled to the register circuit for detecting the positive edge of the target clock; and a negative edge detection circuit including a plurality of negative edge detectors coupled to the register circuit for detecting the negative edge of the target clock, wherein the positive edge detection circuit is operable to perform a logic operation to the target clock levels while the negative edge detection circuit is operable to perform a different logic operation to the target clock levels.

Abstract: The present invention discloses a delay difference detection and adjustment device comprising: a first delay circuit including first delay units to receive and transmit a first clock; a second delay circuit including second delay units to receive and transmit a second clock; a storage circuit including storage units, each of which includes a data input end to receive the first clock and an operation clock reception end to receive the second clock, so that the storage circuit is operable to save a plurality of levels of the first clock according to the second clock; a delay control circuit to adjust the delay amount of the second delay circuit; and an analyzing circuit to generate an analysis result according to the cycle and levels of the first clock in which the analysis result indicates or is used to derive a unit delay difference between the first and second delay units.

Abstract: An element measurement circuit is provided, comprising a oscillator for generating a first oscillation clock and second oscillation clock, a frequency divider for dividing the first oscillation clock to generate a third oscillation clock and for dividing the second oscillation clock to generate a fourth oscillation clock, a frequency detector for detecting the third oscillation clock to generate a first count value and for detecting the fourth oscillation clock to generate a second count value, and a controller for generating a first oscillation period according to the first count value, for generating a second oscillation period according to the second count value, and for generating a measurement value according to the first oscillation period and the second oscillation period.

Abstract: An exemplary scan clock generator for providing a plurality of on-chip scan clocks to a plurality of cells under test includes: a receiving circuit, arranged for receiving an off-chip scan clock; and a clock processing circuit, coupled to the receiving circuit and arranged for generating the on-chip scan clocks according to the received off-chip scan clock; wherein clock edges of the on-chip scan clocks are staggered from each other, and the scan clock generator and the cells under test are set in a same chip.

Abstract: A method for deciding a scan clock domain allocation of an integrated circuit includes: utilizing a circuit netlist file and a timing constraints file of the integrated circuit to find out the amount of crossing paths between any two function clock domains of a plurality of function clock domains, and generate a clock domain report file; and grouping the plurality of function clock domains and allocating the plurality of function clock domains after being grouped into a plurality of scan clock domains according to the clock domain report file.

Abstract: A memory apparatus and a related testing method are provided in the present invention. The memory apparatus includes a memory and a testing module. The testing module includes an error recording unit for recording corresponding addresses of bit errors occurred in the memory. The testing module determines whether the memory has multi-bit error according to the addresses recorded in the error recording unit. The memory is an ECC memory.

Abstract: A method for estimating a clock skew between a first clock and a second clock. The method includes the steps of detecting the clock skew to generate a detection resultant signal representing the clock skew; and determining time unit of a signal processing process, and estimating the clock skew according to the time unit of the signal processing process and the detection resultant signal.

Abstract: The present invention relates to a memory with a self-test function and a method for testing the same. The memory comprises a testing unit, a memory unit, and a comparison module. The method for testing the memory comprises steps of the testing unit producing a pattern signal; a first storage block of the memory unit storing storage data, and outputting the storage data according to the pattern signal; a second storage block of the memory storing a compare signature corresponding to the storage data; and the compare module producing a test signature according to the storage data output by the memory unit, and comparing the test signature to the compare signature and outputting a testing result for judging validity of the memory unit. Thereby, the memory unit according to the present invention is partitioned into two storage blocks for storing the storage data and the compare signature, respectively, and thus achieving the purposes of saving the testing time, costs, and hardware resources.