Patents by Inventor Jih-Shiuan Luo

Jih-Shiuan Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070064353
    Abstract: A method is disclosed for fabricating a read sensor for a magnetic head for a hard disk drive having a read sensor stack and two lateral stacks. The method of fabrication includes forming lateral stacks on a gap layer, surrounding a groove to form a template. The read sensor stack is then formed in the groove, which defines the lateral dimensions of the read sensor stack, and lead layers are then formed on the lateral stacks. Also disclosed is a read head for a disk drive having a sensor stack defined by pre-established lateral stacks, and a disk drive having the read head.
    Type: Application
    Filed: September 20, 2005
    Publication date: March 22, 2007
    Inventors: David Heim, Kim Lee, Tsann Lin, Jih-Shiuan Luo, Chun-Ming Wang
  • Patent number: 7165462
    Abstract: Systems and methods of testing individual sliders are disclosed. One embodiment is a test system that includes a mechanical stress system, a quasi-static measurement system, a transport system, and a slider holder. The individual sliders to be tested are aligned in a row in the slider holder, and the slider holder secures the sliders. The measurement system performs quasi-static measurements on sliders in the slider holder simultaneously. The transport system then transports the slider holder to the mechanical stress system. The mechanical stress system applies mechanical stress to the sliders in slider holder. The transport system then transports the slider holder again to the quasi-static measurement system. This process repeats a desired number of times to complete testing.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: January 23, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Jih-Shiuan Luo, Ali Sanayei
  • Publication number: 20060285259
    Abstract: A method for enhancing thermal stability, improving biasing and reducing damage from electrical surges in self-pinned abutted junction heads. The method includes forming a free layer, forming first hard bias layers abutting the free layer and forming second hard bias layers over the first hard bias layers discontinguous from the free layer, the second hard bias layers being anti-parallel to the first hard bias layers, the first and second hard bias layers providing a net longitudinal bias on the free layer.
    Type: Application
    Filed: July 27, 2006
    Publication date: December 21, 2006
    Inventors: Hardayal Gill, Wen-Chien Hsiao, Jih-Shiuan Luo
  • Patent number: 7099123
    Abstract: A method and apparatus for enhancing thermal stability, improving biasing and reducing damage from electrical surges in self-pinned abutted junction heads. The head includes a sandwiched hard bias layer having a first hard bias layer coupled to a free layer and a second, anti-parallel hard bias layer disposed away form the free layer to provide a net longitudinal bias on the free layer.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: August 29, 2006
    Assignee: Hitachi Global Storage Technologies
    Inventors: Hardayal Singh Gill, Wen-Chien Hsiao, Jih-Shiuan Luo
  • Patent number: 7092220
    Abstract: A method and apparatus for enhancing thermal stability, improving biasing and reducing damage from electrical surges in self-pinned abutted junction heads. A first self-pinned layer having a first magnetic orientation is provided, wherein the first self-pinned layer has a first end, a second end and central portion. A second self-pinned layer is formed over only the central portion of the first self-pinned layer and an interlayer is disposed between the first and second self-pinned layers. A free layer is formed in a central region over the second self-pinned layer. First and second hard bias layers are formed over the first and second ends of the first self-pinned layer respectively, the first and second hard bias layer abutting the free layer, the first and second end of the first self-pinned layer extending under the hard bias layers at the first and second ends.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: August 15, 2006
    Assignee: Hitachi Global Storage Technologies
    Inventors: Hardayal Singh Gill, Wen-Chien Hsiao, Jih-Shiuan Luo
  • Patent number: 7072154
    Abstract: A method and apparatus for enhancing thermal stability, improving biasing and reducing damage from electrical surges in self-pinned abutted junction heads. The head includes a free layer having a first end and a second end defining a width selected to form a desired trackwidth and an extended self-pinned bias layer extending beyond the ends of the free layer, the self-pinned bias layer extending beyond the free layer increasing the volume of the extended self-pinned bias layer to provide greater thermal stability and stronger pinning of the free layer.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: July 4, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Hardayal Singh Gill, Wen-Chien Hsiao, Jih-Shiuan Luo
  • Publication number: 20060112770
    Abstract: Systems and methods of testing individual sliders are disclosed. One embodiment is a test system that includes a mechanical stress system, a quasi-static measurement system, a transport system, and a slider holder. The individual sliders to be tested are aligned in a row in the slider holder, and the slider holder secures the sliders. The measurement system performs quasi-static measurements on sliders in the slider holder simultaneously. The transport system then transports the slider holder to the mechanical stress system. The mechanical stress system applies mechanical stress to the sliders in slider holder. The transport system then transports the slider holder again to the quasi-static measurement system. This process repeats a desired number of times to complete testing.
    Type: Application
    Filed: November 29, 2004
    Publication date: June 1, 2006
    Inventors: Jih-Shiuan Luo, Ali Sanayei
  • Patent number: 7050277
    Abstract: A method and apparatus for enhancing thermal stability, improving biasing and reducing damage from electrical surges in self-pinned abutted junction heads. The head includes a self-pinned layer, the self-pinned layer having a first end, a second end and central portion, a free layer disposed over the central portion of the self-pinned layer in a central region and a first and second hard bias layers formed over the first and second ends of the self-pinned layer respectively, the first and second hard bias layer abutting the free layer, the first and second end of the self-pinned layer extending under the hard bias layers at the first and second ends.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: May 23, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Hardayal Singh Gill, Wen-Chien Hsiao, Jih-Shiuan Luo
  • Patent number: 7049809
    Abstract: A device for handling and testing individual sliders in a row-like format utilizes an elongated, row-like holder having a series of small pockets, each of which receives a single slider. After the sliders enter the holder, a clamp is moved to a closed position to retain the sliders in the holder. The holder is placed in a test fixture such that permanently mounted probes precisely engage the small pads on the sliders for multiple testing purposes. Enlarged probe pads on the test fixture are electrically interconnected with the probes to provide an operator with easy access to the slider pads. The sliders are tested in a row-like format, side by side, to reduce handling-induced electrostatic discharge and mechanical damage.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: May 23, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Jih-Shiuan Luo, Ali Sanayei, Darrick Taylor Smith
  • Patent number: 7019949
    Abstract: In one illustrative example, a spin valve (SV) sensor of the self-pinned type includes a free layer; an antiparallel (AP) self-pinned layer structure; and a non-magnetic electrically conductive spacer layer in between the free layer and the AP self-pinned layer structure. The AP self-pinned layer structure includes a first AP pinned layer having a first thickness; a second AP pinned layer having a second thickness; and an antiparallel coupling (APC) layer formed between the first and the second AP pinned layers. The first thickness is slightly greater than the second thickness. Configured as such, the AP pinned layer structure provides for a net magnetic moment that is in the same direction as a magnetic field produced by the sense current flow, which reduces the likelihood of amplitude flip in the SV sensor.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: March 28, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: James Mac Freitag, Hardayal Singh Gill, Jih-Shiuan Luo, Mustafa Michael Pinarbasi
  • Publication number: 20060061366
    Abstract: A method is disclosed for minimizing damage from electrostatic discharge (ESD) during long-term testing of electronic components and assemblies. The method includes conducting a stress-test, during which a protection circuit is engaged, which shields components and assemblies from ESD. Then at least one functional test is conducted, at which time, the protection circuit is disengaged. Also disclosed is a system for conducting long-term testing of electronic components and assemblies while providing protection from ESD. The system includes a testing circuit for providing current to the components and assemblies during the long-term testing which includes at least one stress-testing phase and at least one functional testing phase. Also included is a protection circuit for protecting the components and assemblies during said stress-testing phase of said long-term testing.
    Type: Application
    Filed: September 23, 2004
    Publication date: March 23, 2006
    Inventor: Jih-Shiuan Luo
  • Patent number: 7005858
    Abstract: A method is disclosed for minimizing damage from electrostatic discharge (ESD) during long-term testing of electronic components and assemblies. The method includes conducting a stress-test, during which a protection circuit is engaged, which shields components and assemblies from ESD. Then at least one functional test is conducted, at which time, the protection circuit is disengaged. Also disclosed is a system for conducting long-term testing of electronic components and assemblies while providing protection from ESD. The system includes a testing circuit for providing current to the components and assemblies during the long-term testing which includes at least one stress-testing phase and at least one functional testing phase. Also included is a protection circuit for protecting the components and assemblies during said stress-testing phase of said long-term testing.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: February 28, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventor: Jih-Shiuan Luo
  • Publication number: 20060012360
    Abstract: A device for handling and testing individual sliders in a row-like format utilizes an elongated, row-like holder having a series of small pockets, each of which receives a single slider. After the sliders enter the holder, a clamp is moved to a closed position to retain the sliders in the holder. The holder is placed in a test fixture such that permanently mounted probes precisely engage the small pads on the sliders for multiple testing purposes. Enlarged probe pads on the test fixture are electrically interconnected with the probes to provide an operator with easy access to the slider pads. The sliders are tested in a row-like format, side by side, to reduce handling-induced electrostatic discharge and mechanical damage.
    Type: Application
    Filed: July 15, 2004
    Publication date: January 19, 2006
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Jih-Shiuan Luo, Ali Sanayei, Darrick Smith
  • Publication number: 20050227184
    Abstract: A method of constructing a small trackwidth magnetorsesistive sensor by defining a trench between first and second hard bias layers and depositing the sensor into the trench.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 13, 2005
    Inventors: David Heim, Kim Lee, Tsann Lin, Jih-Shiuan Luo
  • Publication number: 20050128652
    Abstract: In one illustrative example, a spin valve (SV) sensor of the self-pinned type includes a free layer; an antiparallel (AP) self-pinned layer structure; and a non-magnetic electrically conductive spacer layer in between the free layer and the AP self-pinned layer structure. The AP self-pinned layer structure includes a first AP pinned layer having a first thickness; a second AP pinned layer having a second thickness; and an antiparallel coupling (APC) layer formed between the first and the second AP pinned layers. The first thickness is slightly greater than the second thickness. Configured as such, the AP pinned layer structure provides for a net magnetic moment that is in the same direction as a magnetic field produced by the sense current flow, which reduces the likelihood of amplitude flip in the SV sensor.
    Type: Application
    Filed: December 10, 2003
    Publication date: June 16, 2005
    Inventors: James Freitag, Hardayal Gill, Jih-Shiuan Luo, Mustafa Pinarbasi
  • Patent number: 6879512
    Abstract: A memory device includes a plurality of memory elements each having: an antiferromagnetic layer, a first pinned layer coupled to the antiferromagnetic layer, a nonmagnetic spacer layer coupled to the first pinned layer, a second pinned layer coupled to the spacer, and a free layer coupled to the second pinned layer. A plurality of single wiring circuits are provided, each wiring circuit being coupled to a memory element. An addressing mechanism applies current pulses to the memory elements via the single wiring circuits for writing to the memory elements. The addressing mechanism also applies a sense current to the memory elements via the single wiring circuits for reading the memory elements.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: April 12, 2005
    Assignee: International Business Machines Corporation
    Inventor: Jih-Shiuan Luo
  • Publication number: 20050024784
    Abstract: A method and apparatus for enhancing thermal stability, improving biasing and reducing damage from electrical surges in self-pinned abutted junction heads. The head includes a sandwiched hard bias layer having a first hard bias layer coupled to a free layer and a second, anti-parallel hard bias layer disposed away form the free layer to provide a net longitudinal bias on the free layer.
    Type: Application
    Filed: July 29, 2003
    Publication date: February 3, 2005
    Inventors: Hardayal Gill, Wen-Chien Hsiao, Jih-Shiuan Luo
  • Publication number: 20050024783
    Abstract: A method and apparatus for enhancing thermal stability, improving biasing and reducing damage from electrical surges in self-pinned abutted junction heads. The head includes a self-pinned layer, the self-pinned layer having a first end, a second end and central portion, a free layer disposed over the central portion of the self-pinned layer in a central region and a first and second hard bias layers formed over the first and second ends of the self-pinned layer respectively, the first and second hard bias layer abutting the free layer, the first and second end of the self-pinned layer extending under the hard bias layers at the first and second ends.
    Type: Application
    Filed: July 29, 2003
    Publication date: February 3, 2005
    Inventors: Hardayal Gill, Wen-Chien Hsiao, Jih-Shiuan Luo
  • Publication number: 20050024785
    Abstract: A method and apparatus for enhancing thermal stability, improving biasing and reducing damage from electrical surges in self-pinned abutted junction heads. The head includes a free layer having a first end and a second end defining a width selected to form a desired trackwidth and an extended self-pinned bias layer extending beyond the ends of the free layer, the self-pinned bias layer extending beyond the free layer increasing the volume of the extended self-pinned bias layer to provide greater thermal stability and stronger pinning of the free layer.
    Type: Application
    Filed: July 29, 2003
    Publication date: February 3, 2005
    Inventors: Hardayal Gill, Wen-Chien Hsiao, Jih-Shiuan Luo
  • Publication number: 20050024786
    Abstract: A method and apparatus for enhancing thermal stability, improving biasing and reducing damage from electrical surges in self-pinned abutted junction heads. A first self-pinned layer having a first magnetic orientation is provided, wherein the first self-pinned layer has a first end, a second end and central portion. A second self-pinned layer is formed over only the central portion of the first self-pinned layer and an interlayer is disposed between the first and second self-pinned layers. A free layer is formed in a central region over the second self-pinned layer. First and second hard bias layers are formed over the first and second ends of the first self-pinned layer respectively, the first and second hard bias layer abutting the free layer, the first and second end of the first self-pinned layer extending under the hard bias layers at the first and second ends.
    Type: Application
    Filed: July 29, 2003
    Publication date: February 3, 2005
    Inventors: Hardayal Gill, Wen-Chien Hsiao, Jih-Shiuan Luo