Abstract: A semiconductor package includes a lower semiconductor chip and semiconductor chips in a stack on the lower semiconductor chip in a first direction perpendicular to a top surface of the lower semiconductor chip. Connection bumps are between the lower semiconductor chip and a bottommost one of the semiconductor chips and between the semiconductor chips, A protection layer covers a lateral surface of each of the connection bumps. A mold layer is on the lower semiconductor chip and covering lateral surfaces of the semiconductor chips. The mold layer extends between the bottommost one of the semiconductor chips and the lower semiconductor chip and between the semiconductor chips. The protection layer is between the mold layer and the lateral surface of each of the connection bumps.

Abstract: A carrier substrate and a packaging method, the carrier substrate including a first layer; a second layer; and a first glue layer between the first layer and the second layer, wherein the first glue layer is removably attached to the first layer.

Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.

Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.

Abstract: A semiconductor package can include a substrate and a semiconductor chip on the substrate. A first molding portion can cover the semiconductor chip and can include a first sidewall and a second sidewall opposite each other. A second molding portion can extend on the substrate along the first sidewall and along the second sidewall, where the first molding portion can include a nonconductive material, and the second molding portion can include a conductive material.

Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.

Abstract: A carrier substrate and a packaging method, the carrier substrate including a first layer; a second layer; and a first glue layer between the first layer and the second layer, wherein the first glue layer is removably attached to the first layer.

Abstract: A semiconductor package may include a first semiconductor chip on and electrically connected to a wiring substrate, an intermediate layer on the first semiconductor chip and covering an entire surface of the first semiconductor chip, a second semiconductor chip on the intermediate layer and electrically connected to the wiring substrate, a mold layer on the wiring substrate and covering the first semiconductor chip and the second semiconductor chip, the mold layer including one or more inner surfaces defining a mold via hole that exposes a portion of a surface of the intermediate layer, an electromagnetic shielding layer on the one or more inner surfaces of the mold layer and further on one or more outer surfaces of the mold layer, and a thermal discharge layer on the electromagnetic shielding layer in the mold via hole, such that the thermal discharge layer fills the mold via hole.

Abstract: A semiconductor package can include a substrate and a semiconductor chip on the substrate. A first molding portion can cover the semiconductor chip and can include a first sidewall and a second sidewall opposite each other. A second molding portion can extend on the substrate along the first sidewall and along the second sidewall, where the first molding portion can include a nonconductive material, and the second molding portion can include a conductive material.

Abstract: A semiconductor package includes a circuit board comprising a first surface and a second surface opposite the first surface. A first semiconductor chip is stacked on the first surface and a second semiconductor chip stacked on the first semiconductor chip. A region of the second chip protrudes beyond a side of the first semiconductor chip. A support underpins the protruding region of the second chip. The support may be, for example, dry film solder resist dam.

Abstract: Provided is a semiconductor package that may prevent deformation of stacked semiconductor chips and minimize a semiconductor package size. The semiconductor package includes a package base substrate, a lower chip stacked on the package base substrate, an upper chip stacked on the lower chip, and a first die attach film (DAF) attached to a bottom surface of the upper chip to cover at least a portion of the lower chip. The first DAF may be a multi-layer film including a first attaching layer contacting the bottom surface of the upper chip and a second attaching layer attached to a bottom of the first attaching layer to cover at least a portion of a side surface of the lower chip.

Abstract: Provided is a semiconductor package that may prevent deformation of stacked semiconductor chips and minimize a semiconductor package size. The semiconductor package includes a package base substrate, a lower chip stacked on the package base substrate, an upper chip stacked on the lower chip, and a first die attach film (DAF) attached to a bottom surface of the upper chip to cover at least a portion of the lower chip. The first DAF may be a multi-layer film including a first attaching layer contacting the bottom surface of the upper chip and a second attaching layer attached to a bottom of the first attaching layer to cover at least a portion of a side surface of the lower chip.

Abstract: A package substrate includes a substrate including a top surface and a bottom surface facing each other, the top surface including a first region where a semiconductor chip is mounted and a second region surrounding the first region, and a dummy post on the second region of the top surface to protrude upward from the top surface.

Abstract: A chip-stacked semiconductor package including a stacked chip structure including a plurality of separate chips stacked on each other; a flexible circuit substrate having the stacked chip structure mounted on a first side of the flexible circuit substrate in a first region of the flexible circuit substrate, and being electrically connected to at least one of the plurality of separate chips of the stacked chip structure by folding a second region of the flexible circuit substrate; a sealing portion sealing the stacked chip structure and the flexible circuit substrate; and an external connecting terminal on a second side of the flexible circuit substrate.

Abstract: A semiconductor package includes a circuit board comprising a first surface and a second surface opposite the first surface. A first semiconductor chip is stacked on the first surface and a second semiconductor chip stacked on the first semiconductor chip. A region of the second chip protrudes beyond a side of the first semiconductor chip. A support underpins the protruding region of the second chip. The support may be, for example, dry film solder resist dam.

Abstract: A semiconductor package, a semiconductor device, and a semiconductor module, the semiconductor package including a substrate, the substrate having a plurality of inner pads; a semiconductor chip attached to the substrate, the semiconductor chip being electrically connected to the inner pads; a plurality of lands on the substrate, the plurality of lands being electrically connected to the inner pads; and at least one bypass interconnection on the substrate, wherein the plurality of lands includes a first land and a second land, the bypass interconnection is connected to the first land and the second land, and the first land is spaced apart from the second land by a distance of about three times or greater an average distance between adjacent lands of the plurality of lands.

Abstract: A chip-stacked semiconductor package including a stacked chip structure including a plurality of separate chips stacked on each other; a flexible circuit substrate having the stacked chip structure mounted on a first side of the flexible circuit substrate in a first region of the flexible circuit substrate, and being electrically connected to at least one of the plurality of separate chips of the stacked chip structure by folding a second region of the flexible circuit substrate; a sealing portion sealing the stacked chip structure and the flexible circuit substrate; and an external connecting terminal on a second side of the flexible circuit substrate.

Abstract: A semiconductor package, a semiconductor device, and a semiconductor module, the semiconductor package including a substrate, the substrate having a plurality of inner pads; a semiconductor chip attached to the substrate, the semiconductor chip being electrically connected to the inner pads; a plurality of lands on the substrate, the plurality of lands being electrically connected to the inner pads; and at least one bypass interconnection on the substrate, wherein the plurality of lands includes a first land and a second land, the bypass interconnection is connected to the first land and the second land, and the first land is spaced apart from the second land by a distance of about three times or greater an average distance between adjacent lands of the plurality of lands.

Abstract: Provided is a high-capacity multifunctional multichip package (MCP) structure in which a multifunctional MCP capable of, for example, high-speed image processing and communications, is mounted on a high-capacity memory package capable of storing various data, e.g., moving images, pictures, or music files. The high-capacity memory package may be efficiently applied to a mass storage of a mobile device. However, an eight-stage-plus chip stacking structure should overcome yield loss during assembly and test processes. To do this, a memory package may be divided into a pair of package to form upper and lower package stacks. To physically connect the pair of packages, molding members may be installed opposite each other and fixed to each other using an adhesive member. Also, to electrically connect the pair of packages, one of the packages may be formed using a flexible PCB substrate capable of bending.