Abstract: A method of programming a three-dimensional semiconductor memory device includes applying a first word line programming voltage to a selected word line among the word lines, floating unselected word lines among the word lines, and applying a back-gate pass voltage to the back-gate electrode; applying a first word line verification voltage to the selected word line, applying a word line pass voltage to the unselected word lines, and applying a first back-gate verification voltage to the back-gate electrode; applying a second word line programming voltage to the selected word line, floating the unselected word lines, and applying the back-gate pass voltage to the back-gate electrode; and applying a second word line verification voltage to the selected word line, applying the word line pass voltage to the unselected word lines, and applying a second back-gate verification voltage to the back-gate electrode.

Abstract: A neural network method and device are included, A neural network circuit includes a synaptic memory cell including a resistive memory element, which is disposed along an output line and which can have a first resistance value and a second resistance value as a resistance value, the synaptic memory cell generates a column signal, based on the resistance value of the resistive memory element and an input signal received via an input line, a reference memory cell including a reference memory element, which is disposed along a reference line and which has a resistance value that is a ratio of the first and second resistance values, the reference memory cell generates a reference signal, based on the resistance value of the reference memory element and the input signal, and an output circuit generates an output signal for the output line based on the column signal and the reference signal.

Abstract: A pre-5th-generation (5G) or 5G communication system for supporting higher data rates beyond 4th-generation (4G) communication system, such as a long term evolution (LTE), is provided. A method for performing a beamforming operation in a communication system supporting a frequency division-multiple input multiple output (FD-MIMO) scheme is provided. The method includes detecting a rough beam of a first dominant beam, detecting at least two codeword candidates based on the rough beam of the first dominant beam, and selecting one of the at least two codeword candidates as a final codeword.

Abstract: A method for manufacturing a semiconductor device can reduce congestion across wires while reducing a wire length. The method includes determining a first TSV candidate region in a first die and determining a second TSV candidate region in a second die parallel to the first die. The method also includes determining a first bound region. The first bound region includes a horizontal location of a first pin of the first die and a horizontal location of a second pin of the second die. The method additionally includes calculating an area from overlapped regions between the first bound region and each of the first TSV candidate region and the second TSV candidate region, and performing routing for connecting the first pin and the second pin to each other based on the calculated area.

Abstract: A pre-5th-generation (5G) or 5G communication system for supporting higher data rates beyond 4th-generation (4G) communication system, such as a long term evolution (LTE), is provided. A method for performing a beamforming operation in a communication system supporting a frequency division-multiple input multiple output (FD-MIMO) scheme is provided. The method includes detecting a rough beam of a first dominant beam, detecting at least two codeword candidates based on the rough beam of the first dominant beam, and selecting one of the at least two codeword candidates as a final codeword.

Abstract: A method for manufacturing a semiconductor device can reduce congestion across wires while reducing a wire length. The method includes determining a first TSV candidate region in a first die and determining a second TSV candidate region in a second die perpendicular to the first die, determining a first bound region including a horizontal location of a first pin of the first die and a horizontal location of a second pin of the second die, calculating an area from overlapped regions between the first bound region and each of the first TSV candidate region and the second TSV candidate region, and performing routing for connecting the first pin and the second pin to each other based on the calculated area.