Patents by Inventor Jihong Choi
Jihong Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973019Abstract: Deep trench capacitors (DTCs) in an inter-layer medium (ILM) on an interconnect layer of an integrated circuit (IC) die is disclosed. A method of fabricating an IC die comprising DTCs in the ILM is also disclosed. The DTCs are disposed on an IC, in an ILM, to minimize the lengths of the power and ground traces coupling the DTCs to circuits in a semiconductor layer. The DTCs and the semiconductor layer are on opposite sides of the metal layer(s) used to interconnect the circuits, so the locations of the DTCs in the ILM can be independent of circuit layout and interconnect routing. IC dies with DTCs disposed in the ILM can significantly reduce voltage droop and spikes in IC dies in an IC stack. In one example, DTCs are also located in trenches in the substrate of the IC die.Type: GrantFiled: May 19, 2021Date of Patent: April 30, 2024Assignee: QUALCOMM IncorporatedInventors: Jihong Choi, Stanley Seungchul Song, Giridhar Nallapati, Periannan Chidambaram
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Publication number: 20240107775Abstract: An integrated circuit device includes a plurality of conductive lines on a semiconductor substrate, the plurality of conductive lines extending in a horizontal direction and overlapping each other in a vertical direction, a plurality of insulating layers alternating with the plurality of conductive lines in a vertical direction and extending in the horizontal direction, and a channel structure extending through the plurality of conductive lines and the plurality of insulating layers in the vertical direction. The channel structure includes a core insulating layer, a channel layer on a side wall and a bottom surface of the core insulating layer, an information storage layer on an outside wall of the channel layer, and a pad pattern covering a top surface of the core insulating layer. The pad pattern contacts a portion of the outside wall of the channel layer and a topmost surface of the information storage layer.Type: ApplicationFiled: September 14, 2023Publication date: March 28, 2024Inventors: Hyunmook Choi, Hyunmog Park, JIHONG KIM
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Publication number: 20240079352Abstract: Aspects disclosed herein include integrated circuit (IC) packages employing a capacitor interposer substrate with aligned external interconnects, and related fabrication methods. The IC package includes one or more semiconductor dies (“dies”) electrically coupled to a package substrate that supports electrical signal routing to and from the die(s). The capacitor interposer substrate is disposed between the die(s) and the package substrate. The die(s) is coupled to embedded capacitor(s) in the capacitor interposer substrate through die interconnects coupled to external interconnects of the capacitor interposer substrate. In exemplary aspects, the external interconnects on the outer surfaces of the capacitor interposer substrate are aligned.Type: ApplicationFiled: September 2, 2022Publication date: March 7, 2024Inventors: Jihong Choi, Giridhar Nallapati, Lily Zhao, Dongming He
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Publication number: 20220375851Abstract: Deep trench capacitors (DTCs) in an inter-layer medium (ILM) on an interconnect layer of an integrated circuit (IC) die is disclosed. A method of fabricating an IC die comprising DTCs in the ILM is also disclosed. The DTCs are disposed on an IC, in an ILM, to minimize the lengths of the power and ground traces coupling the DTCs to circuits in a semiconductor layer. The DTCs and the semiconductor layer are on opposite sides of the metal layer(s) used to interconnect the circuits, so the locations of the DTCs in the ILM can be independent of circuit layout and interconnect routing. IC dies with DTCs disposed in the ILM can significantly reduce voltage droop and spikes in IC dies in an IC stack. In one example, DTCs are also located in trenches in the substrate of the IC die.Type: ApplicationFiled: May 19, 2021Publication date: November 24, 2022Inventors: Jihong Choi, Stanley Seungchul Song, Giridhar Nallapati, Periannan Chidambaram
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Publication number: 20220344250Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability.Type: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Inventors: Jihong Choi, Giridhar Nallapati, William Stone, Jianwen Xu, Jonghae Kim, Periannan Chidambaram, Ahmer Syed
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Patent number: 10833017Abstract: A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second portion on the first portion. The semiconductor device also may include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench. The semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench. The conductive material may land in a source/drain region of the semiconductor device.Type: GrantFiled: November 15, 2016Date of Patent: November 10, 2020Assignee: QUALCOMM IncorporatedInventors: Yanxiang Liu, Haining Yang, Youseok Suh, Jihong Choi, Junjing Bao
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Patent number: 9941156Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.Type: GrantFiled: April 1, 2015Date of Patent: April 10, 2018Assignee: QUALCOMM IncorporatedInventors: Shiqun Gu, Vidhya Ramachandran, Christine Sung-An Hau-Riege, John Jianhong Zhu, Jeffrey Junhao Xu, Jihong Choi, Jun Chen, Choh Fei Yeap
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Publication number: 20180076139Abstract: A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second portion on the first portion. The semiconductor device also may include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench. The semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench. The conductive material may land in a source/drain region of the semiconductor device.Type: ApplicationFiled: November 15, 2016Publication date: March 15, 2018Inventors: Yanxiang LIU, Haining YANG, Youseok SUH, Jihong CHOI, Junjing BAO
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Publication number: 20160293475Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.Type: ApplicationFiled: April 1, 2015Publication date: October 6, 2016Inventors: Shiqun Gu, Vidhya Ramachandran, Christine Sung-An Hau-Riege, John Jianhong Zhu, Jeffrey Junhao Xu, Jihong Choi, Jun Chen, Choh Fei Yeap
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Patent number: 9269492Abstract: An orthogonal finger capacitor includes a layer having an anode bone frame adjacent a cathode bone frame, the anode bone frame having a first portion extending along an axis and a second portion extending perpendicular to the axis. A set of anode fingers extends from the first portion. A set of cathode fingers extends from the cathode bone frame, interdigitated with the set of anode fingers. An overlaying layer has another anode bone frame having a first portion parallel to the axis and a perpendicular second portion. A via couples the overlaying anode bone frame to the underlying anode bone frame. The via is located where the first portion of the overlaying anode bone frame overlaps the second portion of the underlying anode bone frame or, optionally, where the second portion of the overlying anode bone frame overlaps the first portion of the underlying anode bone frame.Type: GrantFiled: March 13, 2013Date of Patent: February 23, 2016Assignee: QUALCOMM IncorporatedInventors: John J. Zhu, Pr Chidambaram, Lixin Ge, Bin Yang, Jihong Choi
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Patent number: 9252104Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes a lower interconnect layer of the interconnect stack. The CBC structure also includes a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes a metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure also includes a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having a portion of the first upper interconnect layer, and a second capacitor plate having a portion of the MIM capacitor layer(s).Type: GrantFiled: October 10, 2014Date of Patent: February 2, 2016Assignee: QUALCOMM INCORPORATEDInventors: John J. Zhu, Bin Yang, Pr Chidambaram, Lixin Ge, Jihong Choi
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Patent number: 9245971Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel.Type: GrantFiled: September 27, 2013Date of Patent: January 26, 2016Assignee: QUALCOMM IncorporatedInventors: Bin Yang, P R Chidambaram, John Jianhong Zhu, Jihong Choi, Da Yang, Ravi Mahendra Todi, Giridhar Nallapati, Chock Hing Gan, Ming Cai, Samit Sengupta
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Publication number: 20150091060Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel.Type: ApplicationFiled: September 27, 2013Publication date: April 2, 2015Applicant: QUALCOMM IncorporatedInventors: Bin Yang, PR Chidambaram, John Jianhong Zhu, Jihong Choi, Da Yang, Ravi Mahendra Todi, Giridhar Nallapati, Chock Hing Gan, Ming Cai, Samit Sengupta
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Patent number: 8980708Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).Type: GrantFiled: February 19, 2013Date of Patent: March 17, 2015Assignee: QUALCOMM IncorporatedInventors: John J. Zhu, Bin Yang, P R Chidambaram, Lixin Ge, Jihong Choi
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Publication number: 20150028452Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes a lower interconnect layer of the interconnect stack. The CBC structure also includes a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes a metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure also includes a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having a portion of the first upper interconnect layer, and a second capacitor plate having a portion of the MIM capacitor layer(s).Type: ApplicationFiled: October 10, 2014Publication date: January 29, 2015Inventors: John J. ZHU, Bin YANG, PR CHIDAMBARAM, Lixin GE, Jihong CHOI
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Publication number: 20140231957Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).Type: ApplicationFiled: February 19, 2013Publication date: August 21, 2014Applicant: QUALCOMM INCORPORATEDInventors: John J. Zhu, Bin Yang, PR Chidambaram, Lixin Ge, Jihong Choi
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Publication number: 20140203404Abstract: Spiral metal-on-metal (MoM or SMoM) capacitors and related systems and methods of forming MoM capacitors are disclosed. In one embodiment, a MoM capacitor disposed in a semiconductor die is disclosed. The MoM capacitor comprises a first electrode coupled to a first trace. The first trace is coiled in a first inwardly spiraling pattern and comprised of first parallel trace segments. The MoM capacitor also comprises a second electrode coupled to a second trace. The second trace is coiled in the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments. Reduced variations in the capacitance allow circuit designers to build circuits with tighter tolerances and generally improve circuit reliability.Type: ApplicationFiled: January 21, 2013Publication date: July 24, 2014Applicant: QUALCOMM INCORPORATEDInventors: Jihong Choi, John J. Zhu, PR Chidambaram, Bin Yang, Lixin Ge
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Publication number: 20140197519Abstract: In a particular embodiment, a method of forming a metal-insulator-metal (MIM) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the MIM capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region. The method further includes removing at least a third portion of the insulating layer according to a lift-off technique.Type: ApplicationFiled: January 17, 2013Publication date: July 17, 2014Applicant: QUALCOMM INCORPORATEDInventors: Jihong Choi, John J. Zhu, PR Chidambaram, Bin Yang, Lixin Ge
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Publication number: 20140197520Abstract: In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region. The method further includes removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor.Type: ApplicationFiled: January 17, 2013Publication date: July 17, 2014Applicant: QUALCOMM INCORPORATEDInventors: Jihong Choi, John J. Zhu, Bin Yang, Giridhar Nallapati, PR Chidambaram
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Publication number: 20140092523Abstract: An orthogonal finger capacitor includes a layer having an anode bone frame adjacent a cathode bone frame, the anode bone frame having a first portion extending along an axis and a second portion extending perpendicular to the axis. A set of anode fingers extends from the first portion. A set of cathode fingers extends from the cathode bone frame, interdigitated with the set of anode fingers. An overlaying layer has another anode bone frame having a first portion parallel to the axis and a perpendicular second portion. A via couples the overlaying anode bone frame to the underlying anode bone frame. The via is located where the first portion of the overlaying anode bone frame overlaps the second portion of the underlying anode bone frame or, optionally, where the second portion of the overlying anode bone frame overlaps the first portion of the underlying anode bone frame.Type: ApplicationFiled: March 13, 2013Publication date: April 3, 2014Applicant: QUALCOMM IncorporatedInventors: John J. Zhu, PR Chidambaram, Lixin Ge, Bin Yang, Jihong Choi