Patents by Inventor Ji-hoon Cha

Ji-hoon Cha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11742221
    Abstract: A dry cleaning apparatus includes a chamber, a substrate support supporting a substrate within the chamber, a shower head arranged in an upper portion of the chamber to supply a dry cleaning gas toward the substrate, the shower head including an optical window transmitting a laser light therethrough toward the substrate support, a plasma generator generating plasma from the dry cleaning gas, and a laser irradiator irradiating the laser light on the substrate through the optical window and the plasma to heat the substrate.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: August 29, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Min Shin, Seok-Hoon Kim, Young-Hoo Kim, In-Gi Kim, Tae-Hong Kim, Sung-Hyun Park, Jin-Woo Lee, Ji-Hoon Cha, Yong-Jun Choi
  • Publication number: 20210343552
    Abstract: A dry cleaning apparatus includes a chamber, a substrate support supporting a substrate within the chamber, a shower head arranged in an upper portion of the chamber to supply a dry cleaning gas toward the substrate, the shower head including an optical window transmitting a laser light therethrough toward the substrate support, a plasma generator generating plasma from the dry cleaning gas, and a laser irradiator irradiating the laser light on the substrate through the optical window and the plasma to heat the substrate.
    Type: Application
    Filed: July 15, 2021
    Publication date: November 4, 2021
    Inventors: Seung-Min SHIN, Seok-Hoon KIM, Young-Hoo KIM, In-Gi KIM, Tae-Hong KIM, Sung-Hyun PARK, Jin-Woo LEE, Ji-Hoon CHA, Yong-Jun CHOI
  • Patent number: 11087996
    Abstract: A dry cleaning apparatus includes a chamber, a substrate support supporting a substrate within the chamber, a shower head arranged in an upper portion of the chamber to supply a dry cleaning gas toward the substrate, the shower head including an optical window transmitting a laser light therethrough toward the substrate support, a plasma generator generating plasma from the dry cleaning gas, and a laser irradiator irradiating the laser light on the substrate through the optical window and the plasma to heat the substrate.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Min Shin, Seok-Hoon Kim, Young-Hoo Kim, In-Gi Kim, Tae-Hong Kim, Sung-Hyun Park, Jin-Woo Lee, Ji-Hoon Cha, Yong-Jun Choi
  • Publication number: 20200083063
    Abstract: A dry cleaning apparatus includes a chamber, a substrate support supporting a substrate within the chamber, a shower head arranged in an upper portion of the chamber to supply a dry cleaning gas toward the substrate, the shower head including an optical window transmitting a laser light therethrough toward the substrate support, a plasma generator generating plasma from the dry cleaning gas, and a laser irradiator irradiating the laser light on the substrate through the optical window and the plasma to heat the substrate.
    Type: Application
    Filed: April 1, 2019
    Publication date: March 12, 2020
    Inventors: Seung-Min SHIN, Seok-Hoon KIM, Young-Hoo KIM, In-Gi KIM, Tae-Hong KIM, Sung-Hyun PARK, Jin-Woo LEE, Ji-Hoon CHA, Yong-Jun CHOI
  • Patent number: 10424503
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: September 24, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Patent number: 10090190
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sang Youn, Myung-Geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Publication number: 20180174889
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Application
    Filed: January 31, 2018
    Publication date: June 21, 2018
    Inventors: Young-Sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Patent number: 9972683
    Abstract: A method of fabricating a semiconductor device is provided as follows. A strain relaxed buffer (SRB) layer is formed on a substrate. The SRB layer is formed of a first silicon germanium alloy (SiGe) layer which has a first atomic percent of germanium (Ge) atoms. A heterogeneous channel layer is formed on the SRB layer. The heterogeneous channel layer includes a silicon layer on a first region of the SRB layer and a second SiGe layer on a second region of the SRB layer. The second SiGe layer includes a second atomic percent of germanium greater than the first atomic percent of germanium atoms. The silicon layer is in contact with the second SiGe layer.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: May 15, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Kwon Kim, Ji-Hoon Cha
  • Patent number: 9865597
    Abstract: A semiconductor device is provided as follows. A first fin is formed on a first region of a substrate, extending in a first direction. A second fin is formed on a second region of the substrate, extending in a second direction. A first dual liner is formed on a lateral surface of the first fin. The first dual liner includes a first liner and a second liner. The first liner is interposed between the second liner and the lateral surface of the first fin. A second dual liner is formed on a lateral surface of the second fin. The second dual liner includes a third liner and a fourth liner. The third liner is interposed between the fourth liner and the lateral surface of the second fin. An epitaxial layer surrounds a top portion of the second fin. The first liner and the third liner have different thicknesses.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: January 9, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hoon Cha, Sang-Woo Lee
  • Publication number: 20170301581
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Application
    Filed: June 29, 2017
    Publication date: October 19, 2017
    Inventors: Young-Sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Patent number: 9735156
    Abstract: A semiconductor device including: a fin-type pattern protruding from a substrate and including a first side surface and a second side surface opposite each other; a first trench in contact with the first side surface; a second trench in contact with the second side surface; a first liner formed conformally on a side surface and a bottom surface of the first trench; a first field insulating film disposed on the first liner and partially filling the first trench; a second liner formed conformally on a side surface of the second trench and exposing a bottom surface of the second trench; and a second field insulating film disposed on the second liner and partially filling the second trench.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: August 15, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ji-Hoon Cha
  • Patent number: 9728535
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Publication number: 20170213823
    Abstract: A semiconductor device including: a fin-type pattern protruding from a substrate and including a first side surface and a second side surface opposite each other; a first trench in contact with the first side surface; a second trench in contact with the second side surface; a first liner formed conformally on a side surface and a bottom surface of the first trench; a first field insulating film disposed on the first liner and partially filling the first trench; a second liner formed conformally on a side surface of the second trench and exposing a bottom surface of the second trench; and a second field insulating film disposed on the second liner and partially filling the second trench.
    Type: Application
    Filed: January 26, 2016
    Publication date: July 27, 2017
    Inventor: JI-HOON CHA
  • Publication number: 20170117362
    Abstract: A method of fabricating a semiconductor device is provided as follows. A strain relaxed buffer (SRB) layer is formed on a substrate. The SRB layer is formed of a first silicon germanium alloy (SiGe) layer which has a first atomic percent of germanium (Ge) atoms. A heterogeneous channel layer is formed on the SRB layer. The heterogeneous channel layer includes a silicon layer on a first region of the SRB layer and a second SiGe layer on a second region of the SRB layer. The second SiGe layer includes a second atomic percent of germanium greater than the first atomic percent of germanium atoms. The silicon layer is in contact with the second SiGe layer.
    Type: Application
    Filed: May 3, 2016
    Publication date: April 27, 2017
    Inventors: DONG-KWON KIM, JI-HOON CHA
  • Patent number: 9627514
    Abstract: A method of fabricating a semiconductor device is provided as follows. Epitaxial layers is formed on an active fin structure of a substrate. First metal gate electrodes are formed on the active fin structure. Each first metal gate electrode and each epitaxial layer are alternately disposed in a first direction on the active fin structure. ILD patterns are formed on the epitaxial layers, extending in a second direction crossing the first direction. Sacrificial spacer patterns are formed on the first metal gate electrodes. Each of the plurality of sacrificial spacer patterns covers a corresponding first metal gate electrode of the first metal gate electrodes. Self-aligned contact holes and sacrificial spacers are formed by removing the ILD patterns. Each self-aligned contact hole exposes a corresponding epitaxial layer disposed under each ILD pattern. Source/drain electrodes are formed in the self-aligned contact holes. The sacrificial spacers are replaced with air spacers.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: April 18, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Kwon Kim, Ji-Hoon Cha
  • Patent number: 9613811
    Abstract: A first protective layer, a mask layer, a second protective layer and a photoresist layer are sequentially formed on a substrate. A photoresist pattern is formed by partially removing the photoresist layer. An ion implantation mask is formed by sequentially etching the second protective layer, the mask layer and the first protective layer using the photoresist pattern. The ion implantation mask exposes the substrate. Impurities are implanted in an upper portion of the substrate exposed by the ion implantation mask.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Jik Baek, Sang-Jine Park, Bo-Un Yoon, Young-Sang Youn, Ji-Min Jeong, Ji-Hoon Cha
  • Publication number: 20170069630
    Abstract: A semiconductor device is provided as follows. A first fin is formed on a first region of a substrate, extending in a first direction. A second fin is formed on a second region of the substrate, extending in a second direction. A first dual liner is formed on a lateral surface of the first fin. The first dual liner includes a first liner and a second liner. The first liner is interposed between the second liner and the lateral surface of the first fin. A second dual liner is formed on a lateral surface of the second fin. The second dual liner includes a third liner and a fourth liner. The third liner is interposed between the fourth liner and the lateral surface of the second fin. An epitaxial layer surrounds a top portion of the second fin. The first liner and the third liner have different thicknesses.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 9, 2017
    Inventors: Ji-Hoon CHA, Sang-Woo LEE
  • Publication number: 20170053825
    Abstract: A method for manufacturing a semiconductor device includes forming a first active pattern in a first region of a substrate and a second active pattern in a second region of the substrate, wherein the first and second active patterns project from the substrate, forming a second liner pattern on the substrate and the second active pattern in the second region, wherein the second liner pattern has a second polarity, forming a first liner pattern on the substrate and the first active pattern in the first region, wherein the first liner pattern has a first polarity different from the second polarity, forming an isolation pattern on the first liner pattern in the first region and the second liner pattern in the second region, and exposing the first active pattern and the second active pattern by recessing the isolation pattern.
    Type: Application
    Filed: August 20, 2015
    Publication date: February 23, 2017
    Inventors: KANG-ILL SEO, BOMSOO KIM, JI-HOON CHA
  • Patent number: 9461148
    Abstract: A method of fabricating a semiconductor device is described. The method of fabricating a semiconductor device comprises providing a fin formed to protrude from a substrate and a plurality of gate electrodes formed on the fin to intersect the fin; forming first recesses in the fin on at least one side of the respective gate electrodes; forming an oxide layer on the surfaces of the first recesses; and expanding the first recesses into second recesses by removing the oxide layer. Related devices are also disclosed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 4, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Young Park, Ji-Hoon Cha, Jae-Jik Baek, Bon-Young Koo, Kang-Hun Moon, Bo-Un Yoon
  • Publication number: 20160181243
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Application
    Filed: March 2, 2016
    Publication date: June 23, 2016
    Inventors: Young-sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han