Abstract: An earphone including an audio play portion, a body where a printed circuit board, a plug, and a socket are installed, and a connecting wire. The plug, the socket, and the connecting wire are in electrical connection with the printed circuit board. The plug is configured to be adapted to a lightning interface integrated with an audio output and a power input, and the audio play portion and the socket are in electrical connection with the plug and capable of work simultaneously and being respectively configured to play music and charge when the plug is inserted into the lightning interface. The earphone utilizes the plug to be adapted to the lightning interface integrated with the audio output and the power input.

Abstract: This application provides a data processing system, and the data processing system includes: a Universal Serial Bus (USB) device; a general-purpose processor, deployed with a USB driver; and a dedicated processor, deployed with a first driver, where the first driver is configured to drive a data exchange between the USB device and the dedicated processor, to effectively reduce a transmission delay.

Abstract: An earphone including an audio play portion (30), a body (12) where a printed circuit board (14), a plug (15), and a socket (16) are installed, and a connecting wire (40). The plug (15), the socket (16), and the connecting wire (40) are in electrical connection with the printed circuit board (14). The plug (15) is configured to be adapted to a lightning interface (22) integrated with an audio output and a power input, and the audio play portion (30) and the socket (16) are in electrical connection with the plug (15) and capable of work simultaneously and being respectively configured to play music and charge when the plug (15) is inserted into the lightning interface (22). The earphone utilizes the plug (15) to be adapted to the lightning interface (22) integrated with the audio output and the power input.

Abstract: A method and system for processing correction field information are provided. The method includes: receiving a packet, and obtaining a first correction value carried by the packet; obtaining first time information and second time information; obtaining a second correction value according to the first correction value and the first time information; setting the second correction value in the packet; setting the second time information in the packet; obtaining third time information and fourth time information; obtaining a third correction value according to the second correction value, the second time information, the third time information, and the fourth time information; and setting the third correction value in the packet. The processing of the time information and the processing of the correction field information are performed with a set of processing mechanism, and the implementation is simpler.

Abstract: A method and system for processing correction field information are provided. The method includes: receiving a packet, and obtaining a first correction value carried by the packet; obtaining first time information and second time information; obtaining a second correction value according to the first correction value and the first time information; setting the second correction value in the packet; setting the second time information in the packet; obtaining third time information and fourth time information; obtaining a third correction value according to the second correction value, the second time information, the third time information, and the fourth time information; and setting the third correction value in the packet. The processing of the time information and the processing of the correction field information are performed with a set of processing mechanism, and the implementation is simpler.

Abstract: A method and device for improving clock stability are provided. The method includes: determining whether a difference between a current sender timestamp (ST) and a current receiver timestamp (RT) is a mutated value; pre-processing the ST and RT, if the difference between the ST and RT is a mutated value; acquiring a service clock according to the pre-processed ST and RT; and sending time division multiplex (TDM) data according to the service clock. Through the embodiments of the present disclosure, a packet delay variance (PDV) may be smoothed, the impairment of the PDV on clock recovery may be reduced, the quality of the clock recovery may be improved, and the problem of clock synchronization may be solved through the mutation processing on the timestamps.

Abstract: A precise-clock synchronization method and system and a precise-clock frequency/time synchronization device are provided. In the embodiments of the present invention, two time stamp engines are provided at a slave clock side. A relative time stamp engine provides a relative arrival time stamp. An absolute time stamp engine provides an absolute arrival time stamp. The frequency/time synchronization is calculated by using different time stamps obtained from different time stamp engines, so the frequency synchronization and time synchronization of the master clock and the slave clock may be separately accomplished, and one synchronization function may be enabled or disabled. Therefore, the frequency synchronization and time synchronization of the master clock and the slave clock do not interfere with each other, thus greatly reducing the occupied link bandwidth resources.

Abstract: A method and device for improving clock stability are provided. The method includes: determining whether a difference between a current sender timestamp (ST) and a current receiver timestamp (RT) is a mutated value; pre-processing the ST and RT, if the difference between the ST and RT is a mutated value; acquiring a service clock according to the pre-processed ST and RT; and sending time division multiplex (TDM) data according to the service clock.. Through the embodiments of the present disclosure, a packet delay variance (PDV) may be smoothed, the impairment of the PDV on clock recovery may be reduced, the quality of the clock recovery may be improved, and the problem of clock synchronization may be solved through the mutation processing on the timestamps.

Abstract: A precise-clock synchronization method and system and a precise-clock frequency/time synchronization device are provided. In the embodiments of the present invention, two time stamp engines are provided at a slave clock side. A relative time stamp engine provides a relative arrival time stamp. An absolute time stamp engine provides an absolute arrival time stamp. The frequency/time synchronization is calculated by using different time stamps obtained from different time stamp engines, so the frequency synchronization and time synchronization of the master clock and the slave clock may be separately accomplished, and one synchronization function may be enabled or disabled. Therefore, the frequency synchronization and time synchronization of the master clock and the slave clock do not interfere with each other, thus greatly reducing the occupied link bandwidth resources.

Abstract: A precise-clock synchronization method and system and a precise-clock frequency/time synchronization device are provided. In the embodiments of the present invention, two time stamp engines are provided at a slave clock side. A relative time stamp engine provides a relative arrival time stamp. An absolute time stamp engine provides an absolute arrival time stamp. The frequency/time synchronization is calculated by using different time stamps obtained from different time stamp engines, so the frequency synchronization and time synchronization of master clock and the slave clock may be separately accomplished, and one synchronization function may be enabled or disabled. Therefore, the frequency synchronization and time synchronization of the master clock and the slave clock do not interfere with each other, thus greatly reducing the occupied link bandwidth resources.

Abstract: A method and device for improving clock stability are provided. The method includes: determining whether a difference between a current sender timestamp (ST) and a current receiver timestamp (RT) is a mutated value; pre-processing the ST and RT, if the difference between the ST and RT is a mutated value; acquiring a service clock according to the pre-processed ST and RT; and sending time division multiplex (TDM) data according to the service clock.. Through the embodiments of the present disclosure, a packet delay variance (PDV) may be smoothed, the impairment of the PDV on clock recovery may be reduced, the quality of the clock recovery may be improved, and the problem of clock synchronization may be solved through the mutation processing on the timestamps.

Abstract: A pneumatic pump has a valve body having a piston compartment and a receiving compartment, wherein a piston is slidably and sealedly disposed in the valve body to move between a first position and a second position. The valve body also has an exit opening communicating with the piston compartment and a resilient element to help pushing the piston to the first position. An actuator pumps air into the piston compartment and pushes the piston to the second position. The pneumatic pump further has a valve control which has a sealing member sealedly formed at the piston compartment, a driving member which is connected to the exiting opening, wherein a pressure drives the driving member automatically to unseal the sealing member to release the air inside the piston compartment to a releasing cavity and eventually allows the piston to move back to its original position.