Patents by Inventor Jihun Oh
Jihun Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240046982Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.Type: ApplicationFiled: October 19, 2023Publication date: February 8, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Daero KIM, Kyunghoi Koo, Sujeong Kim, Juyoung Kim, Sanghune Park, Jiyeon Park, Jihun Oh, Kyoungwon Lee
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Patent number: 11830541Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.Type: GrantFiled: January 6, 2022Date of Patent: November 28, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Daero Kim, Kyunghoi Koo, Sujeong Kim, Juyoung Kim, Sanghune Park, Jiyeon Park, Jihun Oh, Kyoungwon Lee
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Publication number: 20220405561Abstract: An electronic device and a controlling method of an electronic device are provided. An electronic device recursively determines a plurality of layers of a neural network model. Weight data of first model information is recursively quantized to obtain a second neural network model. The recursive quantization begins with the weight data and determines an iteration count of a recursion. The recursion operates on error data, quantized weight data, scale data and quantized error data to obtain the iteration count. A first bit-width of the weight data is reduced to a second bit-width of the quantized weight data. The recursion may be performed on a per-layer basis. The weight data may be formulated in a floating-point format and the quantized weight data may be formulated in a fixed point format with an integer number of bits.Type: ApplicationFiled: August 23, 2022Publication date: December 22, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangjeong LEE, Jihun OH, Meejeong PARK
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Publication number: 20220392520Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.Type: ApplicationFiled: January 6, 2022Publication date: December 8, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Daero KIM, Kyunghoi KOO, Sujeong KIM, Juyoung KIM, Sanghune PARK, Jiyeon PARK, Jihun OH, Kyoungwon LEE
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Publication number: 20220121592Abstract: A method of training a physical interface between a first device and a second device includes performing a first training of the physical interface by communicating with the second device by using a first candidate group of lanes from among a plurality of lanes; performing a second training of the physical interface by communicating with the second device by using a second candidate group of lanes from among the plurality of lanes, the second candidate group being different from the first candidate group; determining a lane group based on a result of the first training and a result of the second training; and setting the second device so that the determined lane group is used for the physical interface.Type: ApplicationFiled: September 15, 2021Publication date: April 21, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Taekyung YEO, Sangyun HWANG, Sujeong KIM, Jihun OH, Joohee SHIN
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Publication number: 20220123158Abstract: A photovoltaic (PV) device with improved blue response. The PV device includes a silicon substrate with an emitter layer on a light receiving side. The emitter layer has a low dopant level such that it has sheet resistance of 90 to 170 ohm/sq. Anti-reflection in the PV device is provided solely by a nano-structured or black silicon surface on the light-receiving surface, through which the emitter is fanned by diffusion. The nanostructures of the black silicon are formed in a manner that does not result in gold or another high-recombina-tion metal being left in the black silicon such as with metal-assisted etching using silver. The black silicon is further processed to widen these pores so as to provide larger nanostruc-tures with lateral dimensions in the range of 65 to 150 nanometers so as to reduce surface area and also to etch away a highly doped portion of the emitter.Type: ApplicationFiled: December 23, 2021Publication date: April 21, 2022Inventors: Jihun OH, Howard M. BRANZ, Hao-Chih YUAN
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Patent number: 11251318Abstract: A photovoltaic (PV) device with improved blue response. The PV device includes a silicon substrate with an emitter layer on a light receiving side. The emitter layer has a low opant level such that it has sheet resistance of 90 to 170 ohm/sq. Anti-reflection in the PV device is provided solely by a nano-structured or black silicon surface on the light-receiving surface, through which the emitter is formed by diffusion. The nano structures of the black silicon are formed in a manner that does not result in gold or another high-recombination metal being left in the black silicon such as with metal-assisted etching using silver. The black silicon is further processed to widen these pores so as to provide larger nanostructures with lateral dimensions in the range of 65 to 150 nanometers so as to reduce surface area and also to etch away a highly doped portion of the emitter.Type: GrantFiled: March 8, 2011Date of Patent: February 15, 2022Assignee: Alliance for Sustainable Energy, LLCInventors: Jihun Oh, Howard M. Branz, Hao-Chih Yuan
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Publication number: 20210365779Abstract: An electronic apparatus is provided. The electronic apparatus includes a memory configured to store an artificial intelligence (AI) model including a plurality of layers and a processor, and the AI model may include a plurality of weight values that are scaled based on shift scaling factors different by a plurality of channels included in each of the plurality of layers and quantized by the plurality of layers, and the processor may, based on receiving input data, in a neural network computation process for the input data, compute a channel-wise computation result with an inverse-scaled composite scale parameter based on a shift scaling factor corresponding to each channel.Type: ApplicationFiled: February 9, 2021Publication date: November 25, 2021Inventors: Jihun OH, Sangjeong LEE, Meejeong PARK, Gaurav POONIWALA, Kiseok KWON
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Patent number: 8729798Abstract: Exemplary embodiments are disclosed of anti-reflective nanoporous silicon for efficient hydrogen production by photoelectrolysis of water. A nanoporous black Si is disclosed as an efficient photocathode for H2 production from water splitting half-reaction.Type: GrantFiled: October 28, 2011Date of Patent: May 20, 2014Assignee: Alliance for Sustainable Energy, LLCInventors: Jihun Oh, Howard M. Branz
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Publication number: 20130340824Abstract: A photovoltaic (PV) device with improved blue response. The PV device includes a silicon substrate with an emitter layer on a light receiving side. The emitter layer has a low opant level such that it has sheet resistance of 90 to 170 ohm/sq. Anti-reflection in the PV device is provided solely by a nano-structured or black silicon surface on the light-receiving surface, through which the emitter is formed by diffusion. The nano structures of the black silicon are formed in a manner that does not result in gold or another high-recombination metal being left in the black silicon such as with metal-assisted etching using silver. The black silicon is further processed to widen these pores so as to provide larger nanostructures with lateral dimensions in the range of 65 to 150 nanometers so as to reduce surface area and also to etch away a highly doped portion of the emitter.Type: ApplicationFiled: March 8, 2011Publication date: December 26, 2013Applicant: ALLIANCE FOR SUSTAINABLE ENERGY, LLCInventors: Jihun Oh, Howard M. Branz, Hao-Chih Yuan
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Publication number: 20120103825Abstract: Exemplary embodiments are disclosed of anti-reflective nanoporous silicon for efficient hydrogen production by photoelectrolysis of water. A nanoporous black Si is disclosed as an efficient photocathode for H2 production from water splitting half-reaction.Type: ApplicationFiled: October 28, 2011Publication date: May 3, 2012Applicant: ALLIANCE FOR SUSTAINABLE ENERGY, LLCInventors: Jihun OH, Howard Branz
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Patent number: 7195962Abstract: Provided is a MOSFET with an ultra short channel length and a method of fabricating the same. The ultra short channel MOSFET has a silicon wire channel region with a three-dimensional structure, and a source/drain junction formed in a silicon conductive layer formed of both sides of the silicon wire channel region. Also, a gate electrode formed on the upper surface of the silicon wire channel region by interposing a gate insulating layer having a high dielectric constant therebetween, and source and drain electrodes connected to the source/drain junction are included. The silicon wire channel region is formed with a triangular or trapezoidal section by taking advantage of different etch rates that depend on the planar orientation of the silicon. The source/drain junction is formed by a solid-state diffusion method.Type: GrantFiled: April 27, 2004Date of Patent: March 27, 2007Assignee: Electronics and Telecommunications Research InstituteInventors: Wonju Cho, Seong Jae Lee, Jong Heon Yang, Jihun Oh, Kiju Im, Chang Geun Anh
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Patent number: 6995452Abstract: Provided are an SOI MOSFET device with a nanoscale channel that has a source/drain region including a shallow extension region and a deep junction region formed by solid-phase diffusion and a method of manufacturing the SOI MOSFET device. In the method of manufacturing the MOSFET device, the shallow extension region and the deep junction region that form the source/drain region are formed at the same time using first and second silicon oxide films doped with different impurities. The effective channel length of the device can be scaled down by adjusting the thickness and etching rate of the second silicon oxide film doped with the second impurity. The source/drain region is formed on the substrate before the formation of a gate electrode, thereby easily controlling impurity distribution in the channel. An impurity activation process of the source/drain region can be omitted, thereby preventing a change in a threshold voltage of the device. A solid-phase impurity is diffused.Type: GrantFiled: December 30, 2003Date of Patent: February 7, 2006Assignee: Electronics and Telecommunications Research InstituteInventors: Wonju Cho, Seong Jae Lee, Jong Heon Yang, Jihun Oh, Kiju Im
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Publication number: 20050009250Abstract: Provided is a MOSFET with an ultra short channel length and a method of fabricating the same. The ultra short channel MOSFET has a silicon wire channel region with a three-dimensional structure, and a source/drain junction formed in a silicon conductive layer formed of both sides of the silicon wire channel region. Also, a gate electrode formed on the upper surface of the silicon wire channel region by interposing a gate insulating layer having a high dielectric constant therebetween, and source and drain electrodes connected to the source/drain junction are included. The silicon wire channel region is formed with a triangular or trapezoidal section by taking advantage of different etch rates that depend on the planar orientation of the silicon. The source/drain junction is formed by a solid-state diffusion method.Type: ApplicationFiled: April 27, 2004Publication date: January 13, 2005Inventors: Wonju Cho, Seong Lee, Jong Yang, Jihun Oh, Kiju Im, Chang Anh
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Publication number: 20040203198Abstract: Provided are an SOI MOSFET device with a nanoscale channel that has a source/drain region including a shallow extension region and a deep junction region formed by solid-phase diffusion and a method of manufacturing the SOI MOSFET device. In the method of manufacturing the MOSFET device, the shallow extension region and the deep junction region that form the source/drain region are formed at the same time using first and second silicon oxide films doped with different impurities. The effective channel length of the device can be scaled down by adjusting the thickness and etching rate of the second silicon oxide film doped with the second impurity. The source/drain region is formed on the substrate before the formation of a gate electrode, thereby easily controlling impurity distribution in the channel. An impurity activation process of the source/drain region can be omitted, thereby preventing a change in a threshold voltage of the device. A solid-phase impurity is diffused.Type: ApplicationFiled: December 30, 2003Publication date: October 14, 2004Inventors: Wonju Cho, Seong Jae Lee, Jong Heon Yang, Jihun Oh, Kiju Im