Abstract: A cache memory is shared by N cores of a processor. The cache memory includes a unified tag part and a sliced data part partitioned into N data slices. Each data slice of the N data slices is physically local to a respective one of the N cores and physically remote from the other N?1 cores. N is an integer greater than one. For each core of the N cores, the cache memory biases allocations caused by the core towards a physically local slice of the core. The physically local slice is one of the N data slices and is physically local to the core.

Abstract: Data storage system and management method thereof are provided. The method, adopted by a data storage device coupled to a host device via a bus, includes: determining the data storage device requires to use a first temporary memory of the host device to access data in a second temporary memory of the data storage device; based on the determination, issuing a Device Bus Master (DBM) request message via the bus to the host to request for a right to control data transfer on the bus; in response to the DBM request message, detecting the bus to determine whether to receive a first DBM acknowledgement message from the host device; and if the first DBM acknowledgement message is received, then accessing the first temporary memory of the host device.

Abstract: A universal serial bus (USB) transaction translator is provided along with a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus. At least two buffers are configured to store data. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, with the counting value of the SOF counter being compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves or exceeds the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host.

Abstract: A data transmission system and method are provided. The data transmission method receives a second format data packet sent by a host; decodes the second format data packet sent by the host, and translating the decoded second format data packet into a first format data packet; transmits the first format data packet to a first device; receives a transmission response sent by the first device in response to the first format data packet, determines whether to transmit the transmission response to the host, and performs a re-try flow when the transmission response does not need to be transmitted to the host. Preferably, a data transmission rate of the first device is slower than that of a second device, and the data transmission system is backward compatible to the first device, and the second format data packet is consistent with the second device.

Abstract: A hub device includes an upstream port, multiple downstream ports, a first and a second sub-hub module, a data-format detector, a transaction translator, and a controller. The upstream port is coupled to a host device supporting a first and/or a second data format. Each downstream port is coupled to one of a plurality of slave devices supporting a first and/or a second data format. The first sub-hub module supports transmission of data in the first data format. The second sub-hub module supports transmission of data in the second data format. The data-format detector detects the data format supported by the host device and the slave devices. The transaction translator transforms the data format between the first data format and the second data format. The controller determines whether to control the transaction translator to perform data-format transformation.

Abstract: A data transmission system and method are provided. The data transmission system includes a first link partner and an optical transceiver unit. The first link partner includes a controller. When the first link partner is in an abnormal operation mode, the controller controls the first link partner to exit from the abnormal operation mode. The optical transceiver unit is coupled between the first link partner and a second link partner and performs data transmission between the first link partner and the second link partner. According to the data transmission system and method, one link partner can accurately detect whether another link partner is coupled to the one link partner through an optical transceiver unit. Accordingly, data transmission between the two link partners can be stably performed through the optical transceiver unit.

Abstract: A memory management system and method include and use a cache buffer (such as a table look-aside buffer, TLB), a memory mapping table, a scratchpad cache, and a memory controller. The cache buffer is configured to store a plurality of data structures. The memory mapping table is configured to store a plurality of addresses of the data structures. The scratchpad cache is configured to store the base address of the data structures. The memory controller is configured to control reading and writing in the cache buffer and the scratchpad cache. The components are operable together under control of the memory controller to facilitate effective searching of the data structures in the memory management system.

Abstract: An optical transceiver module adapted to a link device includes a connection unit, a driving unit and optical transmitting and receiving units. The connection unit, to be coupled with the link device, includes an indicating element for generating an indicating signal when the connection unit is coupled with the link device. The driving unit, coupled with the connection unit, receives the indicating signal and outputs a control signal according to the indicating signal. The optical transmitting unit, coupled with the driving unit, receives the control signal for driving the optical transmitting unit to output a first optical signal. The optical receiving unit, coupled with the driving unit, transmits a received second optical signal to the driving unit. An optical transmission device using the optical transceiver module, and an optical transmission method are also disclosed. A link training sequence can be initiated after the connection unit is actually coupled with the link device.

Abstract: An electronic system is provided, in which a smart chip, a smart chip controller, a processor, a system memory, and an access management module is provided. The smart chip controller communicates with the smart chip. The processor performs a mutual authentication with the smart chip. The system memory is accessible to the smart chip and the processor. The access management module is coupled between the processor and the smart chip controller. The access management module prevents the processor accessing a certain range of the system memory according to a block command from the smart chip controller, in response of that the mutual authentication between the processor and the smart chip is failed.

Abstract: The present invention is directed to a transfer request block (TRB) cache system and method. A cache is used to store plural TRBs, and a mapping table is utilized to store corresponding TRB addresses in a system memory. A cache controller pre-fetches the TRBs and stores them in the cache according to the content of the mapping table.

Abstract: A universal serial bus (USB) transaction translator is provided along with a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus. At least two buffers are configured to store data. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, with the counting value of the SOF counter being compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves or exceeds the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host.

Abstract: A data transmission system is provided. The data transmission system includes a first control circuit coupled to a first device, a translation circuit coupled to the first control circuit and a second control circuit coupled to the translation circuit. The first control circuit decodes a first format data packet sent by the first device. The translation circuit receives the decoded first format data packet and translates the decoded first format data packet into a second format data packet. The second control circuit transmits the second format data packet to a host. A data transmission rate of the first device is slower than that of a second device, and the data transmission system is backward compatible to the first device.

Abstract: A data transmission system and method are provided. The data transmission method receives a second format data packet sent by a host; decodes the second format data packet sent by the host, and translating the decoded second format data packet into a first format data packet; transmits the first format data packet to a first device; receives a transmission response sent by the first device in response to the first format data packet, determines whether to transmit the transmission response to the host, and performs a re-try flow when the transmission response does not need to be transmitted to the host. Preferably, a data transmission rate of the first device is slower than that of a second device, and the data transmission system is backward compatible to the first device, and the second format data packet is consistent with the second device.

Abstract: The present invention is directed to a stream context cache system, which primarily includes a cache and a mapping table. The cache stores plural stream contexts, and the mapping table stores associated stream context addresses in a system memory. Consequently, a host may, according to the content of the mapping table, directly retrieve the stream context that is pre-fetched and stored in the cache, rather than read the stream context from the system memory.

Abstract: The present invention is directed to a universal serial bus (USB) transaction translator and a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, wherein the counting value of the SOF counter is compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves the predefined value or is greater than the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time.

Abstract: The present invention is directed to a universal serial bus (USB) transaction translator and an associated IN/OUT bulk transaction method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. In a bulk-IN transaction, before the host sends an IN packet, the controller pre-fetches data and stores the data in the buffers until all the buffers are full or a requested data length has been achieved; the pre-fetched data are then sent to the host after the host sends the IN packet. In a bulk-OUT transaction, the controller stores the data sent from the host in the buffers, and the data are then post-written to the device.

Abstract: A USB host controller is provided. The USB host controller is capable of communicating with multiple USB apparatuses having endpoints and sends a request to a first endpoint. The USB host controller includes a first storage and a first control unit. The first control unit stores endpoint information from the first endpoint into the first storage when the first endpoint issues an unready transaction packet in response to the request. The unready transaction packet indicates that the first endpoint is not ready.

Abstract: An optical transceiver module includes a receiving unit, a transmission driving unit, and a terminal control unit. The receiving unit outputs a receiver lost signal. The transmission driving unit includes a positive receiving signal terminal and a negative receiving signal terminal. The terminal control unit is coupled between the positive receiving signal terminal and the negative receiving signal terminal. The terminal control unit controls whether a differential terminator impedance is coupled between the positive receiving signal terminal and the negative receiving signal terminal according to the receiver lost signal.

Abstract: Power management of a system. A request may be received to enter a first sleep state for a system. One or more processes may be performed to enter the first sleep state in response to the request to enter the first sleep state. A system memory of the system may be stored in a nonvolatile memory (NVM) in response to the request to enter the first sleep state in order to enter a second sleep state. Power may be removed from the system memory after storing the system memory in the NVM in response to the request to enter the first sleep state. After removing power to the system memory, the system may be in the second sleep state.

Abstract: Resuming from a sleep state. A request may received to resume operation of a computer system from a sleep state to an executing state. A restoring process may be initiated to restore the computer system to an executing state. The restoring process may include loading information from a nonvolatile memory medium to a computer system memory medium. A request may be received from a processor of the computer system to access the computer system memory medium. The request may require access to a portion of the computer system memory medium in the executing state, and may be received prior to completion of the restoring process. It may be determined if the portion of the computer system memory medium has been restored. If the portion of the computer system memory medium has not been restored, the portion of the computer system memory medium may be restored from the nonvolatile memory medium ahead of other portions in the restoring process.