Patents by Inventor Jik Ho Cho

Jik Ho Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9786673
    Abstract: A semiconductor memory device may include: a first group of pillars having diameters which are gradually increased toward the a first side; and interlayer insulating layers and conductive patterns surrounding the pillars of the first group, the interlayer insulating layers and conductive patterns being alternately stacked.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: October 10, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jik Ho Cho, Sun Chan Lee
  • Patent number: 8314021
    Abstract: A method for fabricating a semiconductor device includes: forming a thin film over trenches by using a first source gas and a first reaction gas; performing a first post-treatment on the thin film by using a second reaction gas; and performing a second post-treatment on the thin film by using a second source gas.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: November 20, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jik-Ho Cho, Seung-Jin Yeom, Seung-Hee Hong, Nam-Yeal Lee
  • Publication number: 20110244673
    Abstract: A method for fabricating a semiconductor device includes: forming a thin film over trenches by using a first source gas and a first reaction gas; performing a first post-treatment on the thin film by using a second reaction gas; and performing a second post-treatment on the thin film by using a second source gas.
    Type: Application
    Filed: November 3, 2010
    Publication date: October 6, 2011
    Inventors: Jik-Ho CHO, Seung-jin Yeom, Seung-Hee Hong, Nam-Yeal Lee
  • Publication number: 20100164118
    Abstract: A method for fabricating a semiconductor device includes: forming first landing metal contacts over a substrate; forming a plurality of bit lines over the first landing metal contacts, the bit lines insulated from the first landing metal contacts by an inter-layer insulation layer; forming second landing metal through-hole contacts passing between adjacent bit lines to be coupled to the first landing metal contacts; forming metal contacts over the second landing metal contacts; and forming a metal line over the metal contacts.
    Type: Application
    Filed: June 12, 2009
    Publication date: July 1, 2010
    Inventors: Baek-Mann Kim, Seung-Jin Yeom, Jik-Ho Cho
  • Publication number: 20090004864
    Abstract: The present invention relates to a Chemical Mechanical Polishing (CMP) method of a semiconductor device. According to the method, a metal layer is formed over a semiconductor substrate in which an edge region define. A passivation layer is formed on the metal layer. The passivation layer formed in the edge region is etched in order to expose the metal layer. The exposed metal layer is removed through etching. The metal layer is polished by performing a CMP process, thus forming a metal line.
    Type: Application
    Filed: December 27, 2007
    Publication date: January 1, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Tae Kyung Kim, Jik Ho Cho
  • Patent number: 7468317
    Abstract: A method of forming a metal line, in which a nitride layer is used instead of a metal barrier layer, enabling a metal line structure with a relatively low resistance and therefore realizing a high integration of a device. In the method of forming the metal line of the semiconductor device, a first insulating layer and a second insulating layer with a different etch selectivity are sequentially formed on a semiconductor substrate. Predetermined regions of the first insulating layer and the second insulating layer are sequentially etched to form a contact hole. A metal barrier layer is formed on the entire surface including the contact hole. A first metal material is deposited on the entire surface to gap-fill the contact hole. The first metal material on the second insulating layer is stripped such that the first metal material remains only within the contact hole, thus forming a contact plug. A metal line is formed on a predetermined region of the second insulating layer including the contact plug.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: December 23, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jik Ho Cho, Tae Kyung Kim
  • Publication number: 20080200027
    Abstract: The present invention discloses a method of forming a metal wire in a semiconductor device and comprises the steps of forming a first insulating layer, a conductive layer and a capping layer on a semiconductor substrate, forming hard mask patterns on the capping layer, etching the capping layer and the conductive layer through an etching process utilizing the hard mask patterns to form metal wires, removing the hard mask patterns and forming a second insulating layer on the semiconductor substrate including the metal wires to insulate the metal wires from each other.
    Type: Application
    Filed: December 21, 2007
    Publication date: August 21, 2008
    Inventor: Jik Ho Cho
  • Publication number: 20080090411
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes the steps of forming a first insulating film having a contact plug on an upper portion of a semiconductor substrate; forming a second insulating film on an upper portion of the first insulating film and the contact plug; etching the second insulating film formed on the upper portion of the contact plug to expose the upper portion of the contact plug; and, forming a glue film and a metal film on the upper portion of the resulting surface on the semiconductor substrate including the metal wiring contact hole.
    Type: Application
    Filed: May 9, 2007
    Publication date: April 17, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Jik Ho Cho, Tae Kyung Kim
  • Publication number: 20080003808
    Abstract: A method of forming a metal line, in which a nitride layer is used instead of a metal barrier layer, enabling a metal line structure with a relatively low resistance and therefore realizing a high integration of a device. In the method of forming the metal line of the semiconductor device, a first insulating layer and a second insulating layer with a different etch selectivity are sequentially formed on a semiconductor substrate. Predetermined regions of the first insulating layer and the second insulating layer are sequentially etched to form a contact hole. A metal barrier layer is formed on the entire surface including the contact hole. A first metal material is deposited on the entire surface to gap-fill the contact hole. The first metal material on the second insulating layer is stripped such that the first metal material remains only within the contact hole, thus forming a contact plug. A metal line is formed on a predetermined region of the second insulating layer including the contact plug.
    Type: Application
    Filed: November 7, 2006
    Publication date: January 3, 2008
    Applicant: HYNIX SEMICONDUCTOR INC
    Inventors: Jik Ho Cho, Tae Kyung Kim
  • Publication number: 20070281456
    Abstract: A method of forming a line of a semiconductor device, wherein electrical characteristics of the device can be improved by reducing the resistance of the line. According to the method, an amorphous silicide layer or an amorphous TiSiN layer is formed on a semiconductor substrate in which given structures are formed. A line conductive layer is formed on the amorphous silicide layer or the amorphous TiSiN layer.
    Type: Application
    Filed: November 7, 2006
    Publication date: December 6, 2007
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Tae Kyung Kim, Jik Ho Cho
  • Patent number: 7160803
    Abstract: A method of forming a line a semiconductor device, including the steps of forming an interlayer insulating film on a semiconductor substrate in which predetermined structures are formed, forming a trench through which a predetermined region of the semiconductor substrate is exposed in the interlayer insulating film, sequentially forming a glue layer and a first barrier metal film on the entire surface including the trench, forming a second barrier metal film at the bottom of the trench, and forming a line within the trench.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: January 9, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae Kyung Kim, Jik Ho Cho
  • Publication number: 20060189130
    Abstract: A method of forming a line a semiconductor device, including the steps of forming an interlayer insulating film on a semiconductor substrate in which predetermined structures are formed, forming a trench through which a predetermined region of the semiconductor substrate is exposed in the interlayer insulating film, sequentially forming a glue layer and a first barrier metal film on the entire surface including the trench, forming a second barrier metal film at the bottom of the trench, and forming a line within the trench.
    Type: Application
    Filed: June 23, 2005
    Publication date: August 24, 2006
    Inventors: Tae Kyung Kim, Jik Ho Cho