Patents by Inventor Jill Boyce

Jill Boyce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12659493
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to reduce latency during viewport switching in immersive video. An example apparatus include at least one memory, instructions in the apparatus, and processor circuitry to execute the instructions to: obtain a first bitstream having a first encoded frame and a second encoded frame, the second encoded frame encoded at a higher resolution than the first encoded frame and having a coding dependency on the first encoded frame, rewrite the first bitstream into a second bitstream based on field of view information, the second bitstream including a third encoded frame indicative of a portion of the second encoded frame that corresponds to the field of view information and including the first encoded frame, and transmit the second bitstream to a client device for decoding and rendering the portion of the second encoded frame.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: June 16, 2026
    Assignee: Intel Corporation
    Inventors: Gang Shen, Guangxin Xu, Jill Boyce
  • Publication number: 20260122258
    Abstract: A mechanism is described for facilitating defining of interoperability signaling and conformance points for the PCC standard in computing environments. A computing device of embodiments, as described herein, includes a decoder to decode a compressed bitstream of video data representing a point cloud, point cloud reconstructor circuitry to reconstruct a point cloud from the decoded patch video data, a syntax element parser to receive at least one syntax element representing interoperability signaling in the compressed bitstream to indicate the number of points in one or more pictures of the video data, and processing hardware to determine if the number of points in the one or more pictures of the compressed bitstream is within the conformance limits of the point cloud reconstructor circuitry.
    Type: Application
    Filed: December 27, 2024
    Publication date: April 30, 2026
    Applicant: Intel Corporation
    Inventor: Jill Boyce
  • Publication number: 20260112062
    Abstract: Example methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement multi-plane image (MPI) compression are disclosed. Example apparatus disclosed herein include an interface to access an input multiplane image stack corresponding to a source camera viewpoint, the input multiplane image stack including a plurality of texture images and a corresponding plurality of alpha images, ones of the alpha images including pixel values representative of transparency of corresponding pixels in respective ones of the texture images. Disclosed example apparatus also include a compressed image encoder to at least one of (i) convert the plurality of texture images to a single composite texture image to generate a compressed multiplane image stack, or (ii) convert the plurality of alpha images to a single composite alpha image to generate the compressed multiplane image stack. In some disclosed examples, the interface is to output the compressed multiplane image stack.
    Type: Application
    Filed: October 16, 2025
    Publication date: April 23, 2026
    Applicant: Intel Corporation
    Inventors: Scott JANUS, Jill BOYCE, Atul DIVEKAR, Jason TANNER, Sumit BHATIA, Penne Y. LEE
  • Patent number: 12574516
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to encode and decode video using quantization matrices. An example apparatus includes interface circuitry to access an input frame of video, quantization matrix syntax encoder circuitry to encode a set of user-defined quantization matrices into a sequence header associated with a sequence of video frames including the input frame, adaptive quantization matrix selector circuitry to select a subset of quantization matrices from a combination of a set of default quantization matrices and the set of user-defined quantization matrices, adaptive segment selector circuitry to select a first one of the subset of quantization matrices for a first segment of the input frame, the input frame to be divided into a plurality of segments including the first segment, and encoder circuitry to quantize transform coefficients of the first segment of the input frame based on the first one of the subset of quantization matrices.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: March 10, 2026
    Assignee: Intel Corporation
    Inventors: Ximin Zhang, Zhijun Lei, Jill Boyce, Sang-Hee Lee
  • Publication number: 20260067502
    Abstract: Methods, apparatus, systems and articles of manufacture to identify a video decoding error are disclosed. An example apparatus includes an atlas generator to generate atlas data for one or more atlases generated from input views of video; a hash generator to: perform a hash operation on the atlas data to generate a hash value; and include the hash value in a message; and a multiplexer to combine the one or more atlases, coded atlas data corresponding to the atlas data, and the message to generate a video bitstream.
    Type: Application
    Filed: October 16, 2025
    Publication date: March 5, 2026
    Applicant: Intel Corporation
    Inventors: Jill Boyce, Basel Salahieh
  • Publication number: 20260039869
    Abstract: A method comprising: forming an extended field-of-view (FOV) picture; deriving a prediction signal by using the extended-FOV picture; and using the prediction signal to encode at least a part of a current source picture to a current coded picture.
    Type: Application
    Filed: July 31, 2025
    Publication date: February 5, 2026
    Inventors: Miska Matias HANNUKSELA, Jill BOYCE
  • Publication number: 20260012645
    Abstract: Various embodiments provide methods, apparatuses, and computer program products. An example apparatus includes: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: defining a display overlay information message comprising metadata for enabling two or more display overlays to be coded in pictures in one or more layers within a bitstream; and signaling, in or along the bitstream, the display overlay information message to a receiver.
    Type: Application
    Filed: June 24, 2025
    Publication date: January 8, 2026
    Inventors: Jill BOYCE, Miska Matias HANNUKSELA
  • Publication number: 20260012649
    Abstract: An apparatus including: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: allocate a first set of at least one bit of original content of a source picture to a first range of at least one bit; allocate a second set of at least one bit of the original content of the source picture to a second range of at least one bit; form a formed picture comprising a first region based on the first range of at least one bit and a second region based on the second range of at least one bit; code the formed picture into a coded picture.
    Type: Application
    Filed: July 7, 2025
    Publication date: January 8, 2026
    Inventors: Jill BOYCE, Miska Matias HANNUKSELA
  • Publication number: 20260012647
    Abstract: Various embodiments provide methods, apparatuses, and computer program products. An example apparatus includes: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to perform: signaling a constituent rectangle information message without the value of the identifier of the constituent rectangle; and wherein when the value of the identifier is not present in the constituent rectangle information message, the value of the identifier is inferred to be equal to a value of a previously signaled identifier plus a first value.
    Type: Application
    Filed: July 3, 2025
    Publication date: January 8, 2026
    Inventors: Jill BOYCE, Miska Matias HANNUKSELA
  • Publication number: 20260006250
    Abstract: Methods, apparatus, systems and articles of manufacture to generate packed video frames are disclosed. A video encoding system disclosed herein includes a configuration determiner to create a packed video frame layout that includes regions into which video components are to be placed. The system also includes a frame generator to form packed video frames that include the video components placed into different regions. The encoding system further includes a frame information generator that generates packed video frame information that identifies characteristics of the packed video frame including (i) the identities of regions included in the packed video frame layout, (ii) types of video components included in the regions, or iii) information identifying the locations and dimensions of the regions. A video encoder of the encoding system encodes the frames and includes the packed video frame information to signal the inclusion of the packed video frames in the encoded bitstream.
    Type: Application
    Filed: June 30, 2025
    Publication date: January 1, 2026
    Applicant: Intel Corporation
    Inventors: Jill Boyce, Basel Salahieh
  • Publication number: 20250392689
    Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.
    Type: Application
    Filed: August 26, 2025
    Publication date: December 25, 2025
    Applicant: Intel Corporation
    Inventors: Mayuresh VARERKAR, Stanley BARAN, Michael APODACA, Prasoonkumar SURTI, Atsuo KUWAHARA, Narayan BISWAL, Jill BOYCE, Yi-Jen CHIU, Gokcen CILINGIR, Barnan DAS, Atul DIVEKAR, Srikanth POTLURI, Nilesh SHAH, Archie SHARMA
  • Publication number: 20250363674
    Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.
    Type: Application
    Filed: June 11, 2025
    Publication date: November 27, 2025
    Applicant: Intel Corporation
    Inventors: ABHISHEK R. APPU, PRASOONKUMAR SURTI, JILL BOYCE, SUBRAMANIAM MAIYURAN, MICHAEL APODACA, ADAM T. LAKE, JAMES HOLLAND, VASANTH RANGANATHAN, ALTUG KOKER, LIDONG XU, NIKOS KABURLASOS
  • Patent number: 12483701
    Abstract: Disclosed examples include video frame segmenter circuitry to generate segmentation data of first video frame pixel data, the segmentation data including metadata corresponding to a foreground region and a background region, the foreground region corresponding to the first video frame pixel data. The disclosed examples also include video encoder circuitry to generate a first foreground bounding region and a first background bounding region based on the segmentation data, determine a first virtual tile of the first video frame pixel data, the first virtual tile located in the first foreground bounding region, encode the first virtual tile into a video data bitstream without encoding the first background bounding region, and transmit the video data bitstream via a network.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: November 25, 2025
    Assignee: Intel Corporation
    Inventors: Palanivel Guruva reddiar, Jill Boyce, Praveen Nair
  • Patent number: 12470748
    Abstract: Methods, apparatus, systems and articles of manufacture to identify a video decoding error are disclosed. An example apparatus includes an atlas generator to generate atlas data for one or more atlases generated from input views of video; a hash generator to: perform a hash operation on the atlas data to generate a hash value; and include the hash value in a message; and a multiplexer to combine the one or more atlases, coded atlas data corresponding to the atlas data, and the message to generate a video bitstream.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: November 11, 2025
    Assignee: Intel Corporation
    Inventors: Jill Boyce, Basel Salahieh
  • Patent number: 12450780
    Abstract: Example methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement multi-plane image (MPI) compression are disclosed. Example apparatus disclosed herein include an interface to access an input multiplane image stack corresponding to a source camera viewpoint, the input multiplane image stack including a plurality of texture images and a corresponding plurality of alpha images, ones of the alpha images including pixel values representative of transparency of corresponding pixels in respective ones of the texture images. Disclosed example apparatus also include a compressed image encoder to at least one of (i) convert the plurality of texture images to a single composite texture image to generate a compressed multiplane image stack, or (ii) convert the plurality of alpha images to a single composite alpha image to generate the compressed multiplane image stack. In some disclosed examples, the interface is to output the compressed multiplane image stack.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: October 21, 2025
    Assignee: Intel Corporation
    Inventors: Scott Janus, Jill Boyce, Atul Divekar, Jason Tanner, Sumit Bhatia, Penne Y. Lee
  • Publication number: 20250317567
    Abstract: An example apparatus includes: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: form a composite picture from a composition of one or more constituent rectangles; code the composite picture to form a coded composite picture; and signal information related to the composite picture within a supplemental enhancement information message.
    Type: Application
    Filed: April 7, 2025
    Publication date: October 9, 2025
    Inventors: Jill BOYCE, Miska Matias HANNUKSELA
  • Publication number: 20250317573
    Abstract: An example apparatus includes: at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to: determine rectangular regions of a picture; pack the rectangular regions of the picture into a packed picture; code the packed picture; signal the coded packed picture; and signal metadata describing the rectangular regions packed into the coded packed picture.
    Type: Application
    Filed: April 7, 2025
    Publication date: October 9, 2025
    Inventors: Jill BOYCE, Miska Matias HANNUKSELA, Honglei ZHANG
  • Patent number: 12425554
    Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: September 23, 2025
    Assignee: Intel Corporation
    Inventors: Mayuresh Varerkar, Stanley Baran, Michael Apodaca, Prasoonkumar Surti, Atsuo Kuwahara, Narayan Biswal, Jill Boyce, Yi-Jen Chiu, Gokcen Cilingir, Barnan Das, Atul Divekar, Srikanth Potluri, Nilesh Shah, Archie Sharma
  • Publication number: 20250252650
    Abstract: One embodiment provides a graphics processor comprising a block of graphics cores and circuitry including a programmable neural network unit, the programmable neural network unit including one or more neural network hardware blocks, wherein a neural network hardware block includes circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores, wherein the programmable neural network unit is to configure one or more neural network hardware blocks with a meta-shader neural network, the meta-shader neural network to generate a texture for one of multiple types of terrain.
    Type: Application
    Filed: January 9, 2025
    Publication date: August 7, 2025
    Applicant: Intel Corporation
    Inventors: HUGUES LABBE, DARREL PALKE, SHERINE ABDELHAK, JILL BOYCE, VARGHESE GEORGE, SCOTT JANUS, ADAM LAKE, ZHIJUN LEI, ZHENGMIN LI, MIKE MACPHERSON, CARL MARSHALL, SELVAKUMAR PANNEER, PRASOONKUMAR SURTI, KARTHIK VEERAMANI, DEEPAK VEMBAR, VALLABHAJOSYULA SRINIVASA SOMAYAZULU
  • Patent number: 12367654
    Abstract: Devices and techniques related to implementing patch based video coding for machines are discussed. Such patch based video coding includes detecting regions of interest in a frame of video, extracting the detected regions of interest to one or more atlases absent the frame at a resolution not less than the resolution of the regions of interest, and encoding the one or more atlases to a bitstream.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: July 22, 2025
    Assignee: Intel Corporation
    Inventors: Jill Boyce, Palanivel Guruva Reddiar, Praveen Prasad