Abstract: A field programmable gate array circuit device provides a bus interface data path between a processor and system bus, each of which operates at a different data transfer protocol at a different clock rate. The bus interface unit controls the transfer of data to and from a system bus which is connected to a main memory module, an I/O module or other modules, such as an external CPM module. Data passing from various modules to the processor or from the processor to various modules can operate in one word or four-word blocks. Additionally, intermodule communication is managed by message words, which message words are operative in groups of four words as a block. A transfer logic box holds a plurality of (i) Request words (ii) Acknowledgement words for conveyance to the processor from external modules.