Abstract: A device having an encoder and a packet switched video assembler which first estimates how many packets should be generated for one frame based on an estimated frame size and an initial fixed target packet size. Then, an updated packet size is recalculated on a packet-by-packet or slice-by-slice basis. The video assembler includes a three-stage process. The first stage estimates the frame size with or without encoding the video sequence, wherein in the case where the first stage includes encoding, the encoded data is packed in to a simulation bitstream. The second stage estimates the number of packets using the target packet size, estimated frame size and a configuration mode. The third stage dynamically updates the packet size using one-MB look-ahead approach with pre-encoding each MB. In an alternate embodiment, the third stage turns off the look ahead feature when encoding a current macroblock takes place during the third stage.

Abstract: A device having an encoder and a packet switched video assembler which first estimates how many packets should be generated for one frame based on an estimated frame size and an initial fixed target packet size. Then, an updated packet size is recalculated on a packet-by-packet or slice-by-slice basis. The video assembler includes a three-stage process. The first stage estimates the frame size with or without encoding the video sequence, wherein in the case where the first stage includes encoding, the encoded data is packed in to a simulation bitstream. The second stage estimates the number of packets using the target packet size, estimated frame size and a configuration mode. The third stage dynamically updates the packet size using one-MB look-ahead approach with pre-encoding each MB. In an alternate embodiment, the third stage turns off the look ahead feature when encoding a current macroblock takes place during the third stage.