Abstract: A method of making a microelectronic assembly comprises connecting a lead to a contact on a microelectronic element and to a stage. The microelectronic element is juxtaposed with a microelectronic component and the lead is disconnected from the stage. The lead is bonded to a terminal pad on the microelectronic component. A stage for making a microelectronic assembly has a conduit for introducing a bonding tool toward a lead bonded to the stage and extending across the conduit while the microelectronic element is juxtaposed with the microelectronic component.

Abstract: A method of making a microelectronic assembly comprises connecting a lead to a contact on a microelectronic element and to a stage. The microelectronic element is juxtaposed with a microelectronic component and the lead is disconnected from the stage. The lead is bonded to a terminal pad on the microelectronic component. A stage for making a microelectronic assembly has a conduit for introducing a bonding tool toward a lead bonded to the stage and extending across the conduit while the microelectronic element is juxtaposed with the microelectronic component.

Abstract: A method for making a semiconductor chip package. At least one compliant pad is provided on a surface of a substrate and a chip unit is attached to the at least one compliant pad. The at least one compliant pad has a first coefficient of thermal expansion (“CTE”). An encapsulant having a second CTE lower than the CTE of the compliant pads is disposed around the at least one compliant pad to form a composite layer between the chip unit and the substrate.

Abstract: A semiconductor chip package structure for providing a reliable interface between a semiconductor chip and a PWB to accommodate for the thermal coefficient of expansion mismatch therebetween. The interface between a chip and a PWB is comprised of a package substrate having a plurality of compliant pads defining channels therebetween. The package substrate is typically comprised of a flexible dielectric sheet that has leads and terminals on at least one surface thereof. The pads have a first coefficient of thermal expansion (“CTE”) and are comprised of a material having a fairly low modulus of elasticity. An encapsulant having a second CTE lower than the CTE of the compliant pads is disposed within the channels to form a uniform encapsulation layer. The pads are in rough alignment with the conductive terminals on the package substrate thereby allowing independent movement of the terminals during thermal cycling of the chip.