Patents by Inventor Jim C. Chou

Jim C. Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170094284
    Abstract: System and method for improving operational efficiency of a video encoding pipeline used to encode image data. In embodiments, the video encoding pipeline includes bit-rate statistics generation that is useful for controlling subsequent bit rates and/or determining encoding operational modes.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Jim C. Chou, Weichun Ku
  • Publication number: 20170094300
    Abstract: System and method for improving operational efficiency of a video encoding pipeline used to encode image data. In embodiments, the video encoding pipeline includes a transcode pipeline that provides entropy encoding of binarized syntax elements. More specifically, multiple bins may be encoded in parallel, resulting in increased encoding throughput.
    Type: Application
    Filed: March 31, 2016
    Publication date: March 30, 2017
    Inventors: Jim C. Chou, Syed Muhammad Ali Rizvi, Weichun Ku
  • Publication number: 20170094304
    Abstract: System and method for improving operational efficiency of a video encoding pipeline used to encode image data. The video encoding pipeline includes a mode decision block, which selects a first inter-frame prediction mode used to prediction encode a first prediction unit, and a motion estimation block, which receives the first inter-frame prediction mode as feedback from the mode decision block when processing a second prediction unit; determines an initial candidate inter-frame prediction mode of the second prediction unit based at least in part on the first inter-frame prediction mode; and determines a final candidate inter-frame prediction mode of the second prediction unit by performing a first motion estimation search based at least in part on the initial candidate inter-frame prediction mode.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Jim C. Chou, Mark P. Rygh, Guy Côté
  • Publication number: 20170094311
    Abstract: System and method for improving operational efficiency of a video encoding pipeline used to encode image data. In embodiments, the video encoding pipeline includes a low resolution pipeline that includes a low resolution motion estimation block, which generates downscaled image data by reducing resolution of the image data and determines a low resolution inter-frame prediction mode by performing a motion estimation search using the downscaled image data and previously downscaled image data.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Jim C. Chou, Mark P. Rygh, Guy Côté
  • Publication number: 20170094293
    Abstract: System and method for improving operational efficiency of a video encoding pipeline used to encode image data.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Jim C. Chou, Mark P. Rygh, Guy Côté
  • Patent number: 9569816
    Abstract: An image signal processing system may include processing circuitry that may reduce banding artifacts in image data to be depicted on a display. The processing circuitry may receive a first pixel value associated with a first pixel of the image data and detect a first set of pixels located in a first direction along a same row of pixels or a same column of pixels with respect to the first pixel. The first set of pixels is associated with a first band. The processing circuitry may then interpolate a second pixel value based on an average of a first set of pixel values that correspond to the first set of pixels and a distance between the first pixel and a closest pixel in the first band. The processing circuitry may then output the second pixel value for the first pixel.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: February 14, 2017
    Assignee: Apple Inc.
    Inventors: Jim C. Chou, Guy Cote, Haiyan He
  • Patent number: 9571846
    Abstract: Block processing pipeline methods and apparatus in which reference data are stored to a memory according to tile formats to reduce memory accesses when fetching the data from the memory. When the pipeline stores reference data from a current frame being processed to memory as a reference frame, the reference samples are stored in macroblock sequential order. Each macroblock sample set is stored as a tile. Reference data may be stored in tile formats for luma and chroma. Chroma reference data may be stored in tile formats for chroma 4:2:0, 4:2:2, and/or 4:4:4 formats. A stage of the pipeline may write luma and chroma reference data for macroblocks to memory according to one or more of the macroblock tile formats in a modified knight's order. The stage may delay writing the reference data from the macroblocks until the macroblocks have been fully processed by the pipeline.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 14, 2017
    Assignee: Apple Inc.
    Inventors: Timothy John Millet, Mark P. Rygh, Craig M. Okruhlica, Jim C. Chou, Guy Cote, Gaurav S. Gulati, Joseph J. Cheng, Joseph P. Bratt
  • Patent number: 9495731
    Abstract: A method for attenuating banding in image data may involve receiving a stream of input pixels. The method may then include applying a bi-lateral filter to a first portion of the stream of input pixels to generate a first filtered output and applying a high pass filter to a second portion of the stream of input pixels to generate a second filtered output. The method may then determine a local activity and a local intensity associated with the first portion of the stream. The method may then include blending the first filtered output with the first portion of the stream of input pixels based at least in part on the local activity and the local intensity to generate a third filtered output. Afterward, the method may combine the third filtered output with the second filtered output to generate a fourth filtered output that may be output as the image data.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: November 15, 2016
    Assignee: Apple Inc.
    Inventors: Jim C. Chou, Guy Cote, Haiyan He
  • Publication number: 20160307302
    Abstract: A method for attenuating banding in image data may involve receiving a stream of input pixels. The method may then include applying a bi-lateral filter to a first portion of the stream of input pixels to generate a first filtered output and applying a high pass filter to a second portion of the stream of input pixels to generate a second filtered output. The method may then determine a local activity and a local intensity associated with the first portion of the stream. The method may then include blending the first filtered output with the first portion of the stream of input pixels based at least in part on the local activity and the local intensity to generate a third filtered output. Afterward, the method may combine the third filtered output with the second filtered output to generate a fourth filtered output that may be output as the image data.
    Type: Application
    Filed: April 15, 2015
    Publication date: October 20, 2016
    Inventors: Jim C. Chou, Guy Cote, Haiyan He
  • Publication number: 20160307298
    Abstract: An image signal processing system may include processing circuitry that may reduce banding artifacts in image data to be depicted on a display. The processing circuitry may receive a first pixel value associated with a first pixel of the image data and detect a first set of pixels located in a first direction along a same row of pixels or a same column of pixels with respect to the first pixel. The first set of pixels is associated with a first band. The processing circuitry may then interpolate a second pixel value based on an average of a first set of pixel values that correspond to the first set of pixels and a distance between the first pixel and a closest pixel in the first band. The processing circuitry may then output the second pixel value for the first pixel.
    Type: Application
    Filed: April 15, 2015
    Publication date: October 20, 2016
    Inventors: Jim C. Chou, Guy Cote, Haiyan He
  • Patent number: 9473778
    Abstract: The video encoders described herein may make an initial determination to designate a macroblock as a skip macroblock, but may subsequently reverse that decision based on additional information. For example, an initial skip mode decision may be based on aggregate distortion metrics for the luma component of the macroblock (e.g., SAD, SATD, or SSD), then reversed based on an individual pixel difference metric, an aggregate or individual pixel metric for a chroma component of the macroblock, or on the position of the macroblock within a macroblock row. The final skip mode decision may be based, at least in part, on the maximum difference between any pixel in the macroblock (or in a region of interest within the macroblock) and the corresponding pixel in a reference frame. The initial skip mode decision may be made during an early stage of a pipelined video encoding process and reversed in a later stage.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: October 18, 2016
    Assignee: Apple Inc.
    Inventors: Jim C. Chou, Craig M. Okruhlica, Guy Cote
  • Patent number: 9392292
    Abstract: A video encoder may include a context-adaptive binary arithmetic coding (CABAC) encode component that converts each syntax element of a representation of a block of pixels to binary code, serializes it, and codes it mathematically with its probability model, after which the resulting bit stream is output. When the probability of a bin being coded with one of two possible symbols is one-half, the bin may be coded using bypass bin coding mode rather than a more compute-intensive regular bin coding mode. The CABAC encoder may code multiple consecutive bypass bins in a series of cascaded processing units during a single processing cycle (e.g., a regular bin coding cycle). Intermediate outputs of each processing unit may be coupled to inputs of the next processing unit. A resolver unit may accept intermediate outputs of the processing units and generate final output bits for the bypass bins.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 12, 2016
    Assignee: Apple Inc.
    Inventors: Weichun Ku, Jim C. Chou
  • Patent number: 9351003
    Abstract: A video encoder may include a context-adaptive binary arithmetic coding (CABAC) encode component that converts each syntax element of a representation of a block of pixels to binary code, serializes it, and codes it mathematically, after which the resulting bit stream is output. A lookup table in memory and a context cache may store probability values for supported contexts, which may be retrieved from the table or cache for use in coding syntax elements. Depending on the results of a syntax element coding, the probability value for its context may be modified (e.g., increased or decreased) in the cache and, subsequently, in the table. After coding multiple syntax elements, and based on observed access patterns for probability values, a mapping or indexing for the cache or the table may be modified to improve cache performance (e.g., to reduce cache misses or access data for related contexts using fewer accesses).
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: May 24, 2016
    Assignee: Apple Inc.
    Inventors: Guy Cote, Weichun Ku, Jim C. Chou
  • Patent number: 9336558
    Abstract: In the video encoders described herein, blocks of pixels from a video frame may be encoded (e.g., using CAVLC encoding) in a block processing pipeline using wavefront ordering (e.g., in knight's order). Each of the encoded blocks may be written to a particular one of multiple DMA buffers such that the encoded blocks written to each of the buffers represent consecutive blocks of the video frame in scan order. A transcode pipeline may operate in parallel with (or at least overlapping) the operation of the block processing pipeline. The transcode pipeline may read encoded blocks from the buffers in scan order and merge them into a single bit stream (in scan order). A transcoder core of the transcode pipeline may decode the encoded blocks and encode them using a different encoding process (e.g., CABAC). In some cases, the transcoder may be bypassed.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: May 10, 2016
    Assignee: Apple Inc.
    Inventors: Guy Cote, Timothy John Millet, Joseph J. Cheng, Mark P. Rygh, Jim C. Chou
  • Patent number: 9305325
    Abstract: Methods and apparatus for caching neighbor data in a block processing pipeline that processes blocks in knight's order with quadrow constraints. Stages of the pipeline may maintain two local buffers that contain data from neighbor blocks of a current block. A first buffer contains data from the last C blocks processed at the stage. A second buffer contains data from neighbor blocks on the last row of a previous quadrow. Data for blocks on the bottom row of a quadrow are stored to an external memory at the end of the pipeline. When a block on the top row of a quadrow is input to the pipeline, neighbor data from the bottom row of the previous quadrow is read from the external memory and passed down the pipeline, each stage storing the data in its second buffer and using the neighbor data in the second buffer when processing the block.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: April 5, 2016
    Assignee: Apple Inc.
    Inventors: Joseph J. Cheng, Guy Cote, Marc A. Schaub, Jim C. Chou
  • Publication number: 20160021385
    Abstract: Block processing pipeline methods and apparatus in which. motion estimation is performed at a stage of a motion estimation module for a current block with respect to a reference frame at one or more partition sizes to determine candidate motion vectors. The candidate motion vectors may be passed to a next stage for refinement. Motion estimation may then be performed at the next stage to refine the motion vectors. In performing motion estimation at this stage, the input motion vectors of at least one partition size received from the previous stage may be used as candidate motion vectors in searches for at least one other partition size.
    Type: Application
    Filed: July 17, 2014
    Publication date: January 21, 2016
    Applicant: APPLE INC.
    Inventors: Jim C. Chou, Mark P. Rygh
  • Publication number: 20160007046
    Abstract: A component of an entropy encoding stage of a block processing pipeline (e.g., a CABAC encoder) may, for a block of pixels in a video frame, accumulate counts indicating the number of times each of two possible symbols is used in encoding a syntax element bin. An empirical probability for each symbol, an estimated entropy, and an estimated rate cost for encoding the bin may be computed, dependent on the symbol counts. A pipeline stage that precedes the entropy encoding stage may, upon receiving another block of pixels for the video frame, calculate and use the estimated rate cost when making encoding decisions for the other block of pixels based on a cost function that includes a rate cost term. The symbol counts or empirical probabilities may be passed to the earlier pipeline stage or written to a shared memory, from which components of the earlier stage may obtain them.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Applicant: Apple Inc.
    Inventor: Jim C. Chou
  • Publication number: 20160007038
    Abstract: The video encoders described herein may determine an initial designation of a mode in which to encode a block of pixels in an early stage of a block processing pipeline. A component of a late stage of the block processing pipeline (one that precedes the transcoder) may determine a different mode designation for the block of pixels based on coded block pattern information, motion vector information, the position of the block in a row of such blocks, the order in which such blocks are processed in the pipeline, or other encoding related syntax elements. The component in the late stage may communicate information to the transcoder usable in coding the block of pixels, such as modified syntax elements or an end of row marker. The transcoder may encode the block of pixels in accordance with the different mode designation or may change the mode again, dependent on the communicated information.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 7, 2016
    Applicant: APPLE INC.
    Inventors: Jim C. Chou, Guy Cote
  • Patent number: 9224187
    Abstract: Blocks of pixels from a video frame may be encoded in a block processing pipeline using wavefront ordering, e.g. according to knight's order. Each of the encoded blocks may be written to a particular one of multiple buffers such that the blocks written to each of the buffers represent consecutive blocks of the frame in scan order. Stitching information may be written to the buffers at the end of each row. A stitcher may read the rows from the buffers in order and generate a scan order output stream for the frame. The stitcher component may read the stitching information at the end of each row and apply the stitching information to one or more blocks at the beginning of a next row to stitch the next row to the previous row. Stitching may involve modifying pixel(s) of the blocks and/or modifying metadata for the blocks.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 29, 2015
    Assignee: Apple Inc.
    Inventors: Guy Cote, Jim C. Chou, Timothy John Millet, Manching Ko, Weichun Ku
  • Patent number: 9218639
    Abstract: A knight's order processing method for block processing pipelines in which the next block input to the pipeline is taken from the row below and one or more columns to the left in the frame. The knight's order method may provide spacing between adjacent blocks in the pipeline to facilitate feedback of data from a downstream stage to an upstream stage. The rows of blocks in the input frame may be divided into sets of rows that constrain the knight's order method to maintain locality of neighbor block data. Invalid blocks may be input to the pipeline at the left of the first set of rows and at the right of the last set of rows, and the sets of rows may be treated as if they are horizontally arranged rather than vertically arranged, to maintain continuity of the knight's order algorithm.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 22, 2015
    Assignee: Apple Inc.
    Inventors: Guy Cote, Mark P. Rygh, Timothy John Millet, Jim C. Chou, Joseph J. Cheng