Patents by Inventor Jim Chen

Jim Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240312808
    Abstract: An integrated die ejector for separating a die from a wafer, the die ejector includes an ejector mechanism that includes an ejector pin. There is an ejector base coupled to the ejector pin and configured to couple the integrated die ejector to a die attach ejector machine. There is a pepper pot at least partially surrounding the ejector mechanism and ejector base and a sleeve coupled thereto and positioned between the ejector mechanism and pepper pot. The sleeve and pepper pot define an upper and lower motion limit of the ejector base and retain the ejector mechanism within the pepper pot such that the integrated die ejector may be coupled to and decoupled from the die attach ejector machine as a single unit to reduce installation time.
    Type: Application
    Filed: August 3, 2023
    Publication date: September 19, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Simon Yan, JianHua Wang, Kaijian Shi, Bin Liu, Zhonghua Qian, Jim Zhang, Joyce Chen, Juan Zhou
  • Publication number: 20240301099
    Abstract: Ethylene-based polymers having a melt index from 0.8 to 8 g/10 min, a density from 0.94 to 0.96 g/cm3, and a ratio of Mw/Mn from 6 to 20 are disclosed. These polymers can have one or more of an environmental stress crack resistance (ESCR) of at least 5,000 hr (condition A, 100% Igepal), an ESCR of at least 2,500 hr (condition A, 10% Igepal), a CY-a parameter from 0.35 to 0.53, a PSP2 value from 5 to 8.5, a tan ? at 0.1 sec?1 from 8 to 24 degrees, a Mz from 275,000 to 420,000 g/mol, an IVc from 2 to 3 dL/g, a strain hardening modulus (SHM) from 19 to 47 MPa, and/or an amount of polymer eluting between 93 and 95° C. in an ATREF profile of from 7 to 30 wt. %.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 12, 2024
    Inventors: Zhou Chen, Richard M. Buck, Jon D. Ratzlaff, Jeffrey S. Fodor, Jim B. Askew
  • Patent number: 12054501
    Abstract: The disclosure relates to a novel class of compounds that exhibit activity inhibitory activity toward arginase, and pharmaceutical compositions comprising the compounds of the disclosure. Also provided herein are methods of treating cancer with the arginase inhibitors of the disclosure.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: August 6, 2024
    Assignee: Precision Pharmaceuticals, Inc.
    Inventors: Eric B. Sjogren, Jim Li, Lijing Chen, Roland J. Billedeau, Timothy F. Stanton, Michael Van Zandt, Darren Whitehouse, Gunnar E. Jagdmann, Jr., Lene Raunkjaer Petersen
  • Publication number: 20240198499
    Abstract: An impact tool, including a casing, a drive disposed in the casing, a main shaft and a gear assembly connected to the drive, a hammer assembly connected to the gear assembly and main shaft, and an anvil, the main shaft defining a rotation axis around which the hammer assembly and anvil can rotate, the anvil having a head and a stem part, the stem part being substantially cylindrical, and at least one lug extending radially from that end of the stem part which is remote from the head, forming a bottom face substantially perpendicular to the rotation axis R; the anvil further includes a guide part extending axially from that end of the stem part which is remote from the head, and a front end of the main shaft is accommodated in the guide part.
    Type: Application
    Filed: March 1, 2021
    Publication date: June 20, 2024
    Inventors: Cheu Chyong TEH, Quirin WAHLE, Jim CHEN
  • Patent number: 11748850
    Abstract: Embodiments relate to a super-resolution engine that converts a lower resolution input image into a higher resolution output image. The super-resolution engine includes a directional scaler, an enhancement processor, a feature detection processor, a blending logic circuit, and a neural network. The directional scaler generates directionally scaled image data by upscaling the input image. The enhancement processor generates enhanced image data by applying an example-based enhancement, a peaking filter, or some other type of non-neural network image processing scheme to the directionally scaled image data. The feature detection processor determines features indicating properties of portions of the directionally scaled image data. The neural network generates residual values defining differences between a target result of the super-resolution enhancement and the directionally scaled image data. The blending logic circuit blends the enhanced image data with the residual values according to the features.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: September 5, 2023
    Assignee: Apple Inc.
    Inventors: Jim Chen Chou, Chenge Li, Yun Gong
  • Publication number: 20230150099
    Abstract: A socket holding device for a power tool includes an anvil with a drive square head, a holding bolt, and a stop pin. The holding bolt locks a tool element that is clipped on the drive square head and the holding bolt is supportable elastically in a recessed seat of the drive square head such that the holding bolt is moveable perpendicularly to a rotation axis of the anvil. The stop pin is disposable in a mounting hole of the drive square head and the holding bolt is lockable by the stop pin when the holding bolt is supported elastically in the recessed seat of the drive square head and the stop pin is disposed in the mounting hole. The stop pin has a first portion partially clippable on the holding bolt and a diameter of the first portion is larger than an inner diameter of the mounting hole.
    Type: Application
    Filed: March 16, 2021
    Publication date: May 18, 2023
    Inventor: Jim CHEN
  • Publication number: 20220270208
    Abstract: Embodiments relate to a super-resolution engine that converts a lower resolution input image into a higher resolution output image. The super-resolution engine includes a directional scaler, an enhancement processor, a feature detection processor, a blending logic circuit, and a neural network. The directional scaler generates directionally scaled image data by upscaling the input image. The enhancement processor generates enhanced image data by applying an example-based enhancement, a peaking filter, or some other type of non-neural network image processing scheme to the directionally scaled image data. The feature detection processor determines features indicating properties of portions of the directionally scaled image data. The neural network generates residual values defining differences between a target result of the super-resolution enhancement and the directionally scaled image data. The blending logic circuit blends the enhanced image data with the residual values according to the features.
    Type: Application
    Filed: April 15, 2022
    Publication date: August 25, 2022
    Inventors: Jim Chen Chou, Chenge Li, Yun Gong
  • Patent number: 11308582
    Abstract: Embodiments relate to a super-resolution engine that converts a lower resolution input image into a higher resolution output image. The super-resolution engine includes a directional scaler, an enhancement processor, a feature detection processor, a blending logic circuit, and a neural network. The directional scaler generates directionally scaled image data by upscaling the input image. The enhancement processor generates enhanced image data by applying an example-based enhancement, a peaking filter, or some other type of non-neural network image processing scheme to the directionally scaled image data. The feature detection processor determines features indicating properties of portions of the directionally scaled image data. The neural network generates residual values defining differences between a target result of the super-resolution enhancement and the directionally scaled image data. The blending logic circuit blends the enhanced image data with the residual values according to the features.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: April 19, 2022
    Assignee: Apple Inc.
    Inventors: Jim Chen Chou, Chenge Li, Yun Gong
  • Patent number: 11308098
    Abstract: A system and method for translating and matching attributes in data records that describe travel items is provided. In an embodiment, a plurality of records is received from a plurality of data sources. Record parsing logic is used divide strings in the records into individual words and match single words in the plurality of records to attributes. Using the matched attributes, record comparison logic creates a confidence score that describes the likelihood that two records describe the same listing or inventory item. If the confidence score exceeds a given threshold, the records are determined to match. A consolidated record is then created from the two matched records.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: April 19, 2022
    Assignee: priceline.com LLC
    Inventors: Amit Poddar, Michael Diliberto, John Caine, Jim Chen, Will Homes, Nasreen Ali, Murali Gadde, Ian Merritt, Ronald Henderson, Christine Wong
  • Patent number: 10970653
    Abstract: A system and method for actively updating a data cache is provided. In an embodiment, a plurality of travel listings is received from a plurality of data sources and stored in a data cache. Invalidity prediction instructions are used to determine that a travel listing in the data cache contains inaccurate information. Listing relationship instructions are used to identify listings that are related to the travel listing that contains inaccurate information. Data update requests are then sent to the plurality of data sources for the related listings.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: April 6, 2021
    Assignee: PRICELINE.COM LLC
    Inventors: Amit Poddar, Michael Diliberto, John Caine, Jim Chen, Will Homes, Nasreen Ali, Murali Gadde, Ian Merritt, Ronald Henderson, Christine Wong
  • Patent number: 10802973
    Abstract: An apparatus includes a first database, a memory, and first and second processors. The first database stores a list including a first identifier assigned to the first processor and a second identifier assigned to the second processor. The processors each randomly shuffle a copy of the list and place the first element of their shuffled copy in a third list. Each processor further determines that the first identifier appears a first number of times and the second identifier appears a second number of times in the third list, the first number greater than the second number. In response to determining that the first number is greater than the second number, the first processor copies data stored in a second database into the memory and sets a flag to true, while the second processor determines that the flag is set to true and accesses the data copy stored in the memory.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: October 13, 2020
    Assignee: Bank of America Corporation
    Inventors: Udaya Kumar Raju Ratnakaram, Niroop Reddy Patimeedi, Sarvari Tadimalla, Maruthi Shanmugam, Jian Jim Chen, Punit Srivastava
  • Publication number: 20200294196
    Abstract: Embodiments relate to a super-resolution engine that converts a lower resolution input image into a higher resolution output image. The super-resolution engine includes a directional scaler, an enhancement processor, a feature detection processor, a blending logic circuit, and a neural network. The directional scaler generates directionally scaled image data by upscaling the input image. The enhancement processor generates enhanced image data by applying an example-based enhancement, a peaking filter, or some other type of non-neural network image processing scheme to the directionally scaled image data. The feature detection processor determines features indicating properties of portions of the directionally scaled image data. The neural network generates residual values defining differences between a target result of the super-resolution enhancement and the directionally scaled image data. The blending logic circuit blends the enhanced image data with the residual values according to the features.
    Type: Application
    Filed: April 9, 2020
    Publication date: September 17, 2020
    Inventors: Jim Chen Chou, Chenge Li, Yun Gong
  • Patent number: 10621697
    Abstract: Embodiments relate to a super-resolution engine that converts a lower resolution input image into a higher resolution output image. The super-resolution engine includes a directional scaler, an enhancement processor, a feature detection processor, a blending logic circuit, and a neural network. The directional scaler generates directionally scaled image data by upscaling the input image. The enhancement processor generates enhanced image data by applying an example-based enhancement, a peaking filter, or some other type of non-neural network image processing scheme to the directionally scaled image data. The feature detection processor determines features indicating properties of portions of the directionally scaled image data. The neural network generates residual values defining differences between a target result of the super-resolution enhancement and the directionally scaled image data. The blending logic circuit blends the enhanced image data with the residual values according to the features.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: April 14, 2020
    Assignee: Apple Inc.
    Inventors: Jim Chen Chou, Chenge Li, Yun Gong
  • Publication number: 20200043135
    Abstract: Embodiments relate to a super-resolution engine that converts a lower resolution input image into a higher resolution output image. The super-resolution engine includes a directional scaler, an enhancement processor, a feature detection processor, a blending logic circuit, and a neural network. The directional scaler generates directionally scaled image data by upscaling the input image. The enhancement processor generates enhanced image data by applying an example-based enhancement, a peaking filter, or some other type of non-neural network image processing scheme to the directionally scaled image data. The feature detection processor determines features indicating properties of portions of the directionally scaled image data. The neural network generates residual values defining differences between a target result of the super-resolution enhancement and the directionally scaled image data. The blending logic circuit blends the enhanced image data with the residual values according to the features.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 6, 2020
    Inventors: Jim Chen Chou, Chenge Li, Yun Gong
  • Publication number: 20200019556
    Abstract: A system and method for translating and matching attributes in data records that describe travel items is provided. In an embodiment, a plurality of records is received from a plurality of data sources. Record parsing logic is used divide strings in the records into individual words and match single words in the plurality of records to attributes. Using the matched attributes, record comparison logic creates a confidence score that describes the likelihood that two records describe the same listing or inventory item. If the confidence score exceeds a given threshold, the records are determined to match. A consolidated record is then created from the two matched records.
    Type: Application
    Filed: September 23, 2019
    Publication date: January 16, 2020
    Inventors: Amit Poddar, Michael Diliberto, John Caine, Jim Chen, Will Homes, Nasreen Ali, Murali Gadde, Ian Merritt, Ronald Henderson, Christine Wong
  • Patent number: 10430423
    Abstract: A system and method for translating and matching attributes in data records that describe travel items is provided. In an embodiment, a plurality of records is received from a plurality of data sources. Record parsing logic is used divide strings in the records into individual words and match single words in the plurality of records to attributes. Using the matched attributes, record comparison logic creates a confidence score that describes the likelihood that two records describe the same listing or inventory item. If the confidence score exceeds a given threshold, the records are determined to match. A consolidated record is then created from the two matched records.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: October 1, 2019
    Assignee: priceline.com LLC
    Inventors: Amit Poddar, Michael Diliberto, John Caine, Jim Chen, Will Homes, Nasreen Ali, Murali Gadde, Ian Merritt, Ronald Henderson, Christine Wong
  • Patent number: 10367580
    Abstract: A coaxial cable tap comprises a housing, and a faceplate coupled to the housing. The faceplate comprises a first directional tap port, and a diagnostic reverse (DR) port configured to receive a first upstream signal originating downstream from the coaxial cable tap, and inject a downstream test signal in a downstream direction. A hybrid fiber-coaxial (HFC) network comprises a headend, a first amplifier coupled to the headend, and a tap coupled to the first amplifier, configured to couple to a plurality of cable modems (CMs), and comprising a diagnostic forward (DF) port configured to receive a downstream signal originating from the first amplifier, and inject an upstream test signal in an upstream direction for reception at the headend.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: July 30, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: John L. Moran, III, Liming Fang, Jim Chen, Li Zhang, Xiaolong Zhang, Karl E. Moerder, Marc L. Morrissette
  • Patent number: 10057667
    Abstract: A method implemented by a middlebox comprising registering a customer premises equipment (CPE) in the middlebox, wherein the CPE is coupled to the middlebox via an electrical line, and facilitating registration of the CPE in a central office (CO) equipment coupled to the middlebox.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: August 21, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Liming Fang, Jim Chen, Li Zhang
  • Patent number: 9948457
    Abstract: An optical line terminal (OLT) including a processor coupled to a transmitter. The processor is configured to send a first encrypted fiber to coax unit (FCU) message containing an optical domain multicast key to an FCU via an optical network. The optical domain multicast key is associated with encryption in an optical domain associated with the optical network. The processor is also configured to send a second encrypted FCU message containing an electrical domain multicast key to the FCU, and to send an encrypted coax network unit (CNU) message containing the electrical domain multicast key to a CNU via the FCU and a coaxial network. The electrical domain multicast key is associated with encryption in an electrical domain associated with the coaxial network. The first and second encrypted FCU messages and the encrypted CNU message may be operations, administration and maintenance (OAM) messages.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: April 17, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Yanbin Sun, Guangsheng Wu, Li Zhang, Fanglin Sun, Jim Chen
  • Patent number: 9838363
    Abstract: A method comprising generating an updated security key upon expiration of a key exchange timer, transferring the updated security key to a Coaxial Network Unit (CNU), retaining an original key, wherein the updated security key comprises a different key identification number than the original key, accepting and decrypting upstream traffic that employs either the original key or the updated key, after transferring the updated security key to the CNU, creating a key switchover timer, before the key switchover timer expires, verify that upstream traffic transferred from the CNU on a logical link uses the updated security key, and when upstream traffic is encrypted using the updated security key, begin using the updated security key to encrypt downstream traffic and clear the key switchover timer.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: December 5, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventors: Yanbin Sun, Guangsheng Wu, Li Zhang, Jim Chen