Abstract: A synchronous vector processor SVP device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and is capable of real-time digital processing of video signals. The SVP includes interconnecting circuitry enabling the individual processor elements to retrieve data from and transmit data to their first and second nearest neighbors on either side. At the chip level external connections are provided to enable cascading of several SVP devices.

Abstract: A redundancy scheme for a memory device, as well as a method for developing a redundancy scheme, resulting in improved repairability for given space constraints. A memory device is formed with a plurality of data blocks having individual input/output paths. Each block comprises an array of memory cells arranged in addressable rows and columns along row lines and column lines. The array is configured in sub-blocks each comprising a plurality of the memory cells. The device includes row address circuitry for selecting a row of the memory cells, column address circuitry for selecting a column of the memory cells and address repair circuitry. The address repair circuitry is configurable to render a first portion of a first of the columns of cells responsive to the address of a portion of a second of the columns of cells. There is also provided a method for eliminating a defect in a memory device having a logical data block formed with addressable rows and columns of memory cells.