Abstract: An apparatus includes memory cells programmed to one of a plurality of data states, wherein the memory cells are configured such that the plurality of data states comprise an error-prone data state. Sense circuitry of the apparatus is configured to sense first memory cells programmed to the error-prone data state, determine a bit encoding for the first memory cells, sense other memory cells programmed to other data states, and determine a bit encoding for the other memory cells. A communication circuit of the apparatus is configured to communicate the bit encoding for the other memory cells, the bit encoding for the first memory cells, and an indication that the first memory cells are programmed to the error-prone data state, in response to a single read command from a controller.

Abstract: An apparatus includes memory cells programmed to one of a plurality of data states, wherein the memory cells are configured such that the plurality of data states comprise an error-prone data state. Sense circuitry of the apparatus is configured to sense first memory cells programmed to the error-prone data state, determine a bit encoding for the first memory cells, sense other memory cells programmed to other data states, and determine a bit encoding for the other memory cells. A communication circuit of the apparatus is configured to communicate the bit encoding for the other memory cells, the bit encoding for the first memory cells, and an indication that the first memory cells are programmed to the error-prone data state, in response to a single read command from a controller.

Abstract: An apparatus includes memory cells programmed to one of a plurality of data states, wherein the memory cells are configured such that the plurality of data states comprise an error-prone data state. Sense circuitry of the apparatus is configured to sense first memory cells programmed to the error-prone data state, determine a bit encoding for the first memory cells, sense other memory cells programmed to other data states, and determine a bit encoding for the other memory cells. A communication circuit of the apparatus is configured to communicate the bit encoding for the other memory cells, the bit encoding for the first memory cells, and an indication that the first memory cells are programmed to the error-prone data state, in response to a single read command from a controller.

Abstract: A non-volatile memory system includes a plurality of groups of connected non-volatile memory cells (e.g., charge trapping memory cells), a select line, and a plurality of select gates connected to the select line. Each select gate is connected at an end (e.g. source end or drain side) of one of the groups of memory cells. The system includes one or more control circuits that are configured to determine whether the select gates are abnormal. If a select gate is determined to be abnormal, then one of the memory cells connected to the select gate is converted to operate as a select gate. The system will then perform memory operations by operating the converted memory cell as a select gate.

Abstract: A non-volatile memory system includes a plurality of groups of connected non-volatile memory cells (e.g., charge trapping memory cells), a select line, and a plurality of select gates connected to the select line. Each select gate is connected at an end (e.g. source end or drain side) of one of the groups of memory cells. The system includes one or more control circuits that are configured to determine whether the select gates are abnormal. If a select gate is determined to be abnormal, then one of the memory cells connected to the select gate is converted to operate as a select gate. The system will then perform memory operations by operating the converted memory cell as a select gate.

Abstract: An actuation efficiency for a head is determined based on a displacement of the head relative to a storage media responsive to excitation of a heater element. Damage to the head is detected based on the determined actuation efficiency. Related circuits and devices are also discussed.

Abstract: A read/write channel for a hard disk drive comprising at least one analog read component and a fly height control system. The fly height control system controls fly height based on a current fly height value generated based on a fly height measurement signal that passes through the at least one analog read component. The read/write channel comprises a calibration signal generator and a processor. The calibration signal generator generates a calibration signal that is coupled to the at least analog read component to place the read/write channel in a calibration mode. The processor generates compensation data based on an output of the at least one analog read component when the read/write channel is in the calibration mode. The processor generates the current fly height value based on the fly height measurement signal and the compensation data when the read/write channel is in a fly height measurement mode.

Abstract: Write commands through a read/write head are regulated in response to head fly height. The head fly height is determined, and the rate at which the write command is carried out is regulated in response to the determined fly height. The rate may be regulated by inserting write inhibit gaps between writing data segments of the write command so as to allow the head to cool and, thereby, control fly height.

Abstract: Various embodiments are disclosed that control head fly height based on estimates of head fly height. The fly height clearance between the head and a data storage media is estimated. Heating of the head by a heater element is then regulated in response to the estimated fly height.

Abstract: An actuation efficiency for a head is determined based on a displacement of the head relative to a storage media responsive to excitation of a heater element. Damage to the head is detected based on the determined actuation efficiency. Related circuits and devices are also discussed.

Abstract: Various embodiments are disclosed that control head fly height based on estimates of head fly height. The fly height clearance between the head and a data storage media is estimated. Heating of the head by a heater element is then regulated in response to the estimated fly height.

Abstract: Write commands through a read/write head are regulated in response to head fly height. The head fly height is determined, and the rate at which the write command is carried out is regulated in response to the determined fly height. The rate may be regulated by inserting write inhibit gaps between writing data segments of the write command so as to allow the head to cool and, thereby, control fly height.

Abstract: Synchronous detection of fine position servo burst information with a data transducer having an electrical width not less than about two-thirds a width of a data track within a partial response maximum likelihood (PRML) data channel is disclosed. The servo burst information is recorded on a storage medium as a pair or series of fractional-track-width sinewave concurrent burst patterns and includes an on-track phase generating a position error signal which varies linearly with head displacement about track centerline and at least one off-track phase generating a position error signal which varies linearly with head displacement about a position related to track boundary.