Patents by Inventor Jim Holt

Jim Holt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070120184
    Abstract: An HV PMOS device formed on a substrate having an HV well of a first polarity type formed in an epitaxial layer of a second polarity type includes a pair of field oxide regions on the substrate and at least partially over the HV well. Insulated gates are formed on the substrate between the field oxide regions. Stacked hetero-doping rims are formed in the HV well and in self-alignment with outer edges of the gates. A buffer region of the first polarity type is formed in the HV well between and in self-alignment with inner edges of the gates. A drift region of the second polarity type is formed in the buffer region between and in self-alignment with inner edges of the gates. The drift region includes a region having a gradual dopant concentration change, and includes a drain region of the second polarity type.
    Type: Application
    Filed: January 31, 2007
    Publication date: May 31, 2007
    Inventors: Jun Cai, Michael Harley-Stead, Jim Holt
  • Publication number: 20070040212
    Abstract: An asymmetric heterodoped metal oxide (AH2MOS) semiconductor device includes a substrate and an insulated gate on the top of the substrate disposed between a source region and a drain region. On one side of the gate, heterodoped tub and source regions are formed. The tub region has dopants of a second polarity. A source region is disposed inside each tub region and has dopants of a first polarity opposite to the second polarity. On the other side of the gate, heterodoped buffer and drift regions are formed. The buffer regions comprise dopants of the second polarity. The drift regions are disposed inside the buffer regions and are doped with dopants of the first polarity. A drain n+ tap region is disposed in the drift region.
    Type: Application
    Filed: October 23, 2006
    Publication date: February 22, 2007
    Inventors: Jun Cai, Michael Harley-Stead, Jim Holt
  • Publication number: 20070018250
    Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.
    Type: Application
    Filed: May 15, 2006
    Publication date: January 25, 2007
    Inventors: Jun Cai, Micheal Harley-Stead, Jim Holt
  • Publication number: 20060118814
    Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.
    Type: Application
    Filed: December 7, 2004
    Publication date: June 8, 2006
    Inventors: Jun Cai, Micheal Harley-Stead, Jim Holt
  • Publication number: 20060057784
    Abstract: An HV PMOS device formed on a substrate having an HV well of a first polarity type formed in an epitaxial layer of a second polarity type includes a pair of field oxide regions on the substrate and at least partially over the HV well. Insulated gates are formed on the substrate between the field oxide regions. Stacked hetero-doping rims are formed in the HV well and in self-alignment with outer edges of the gates. A buffer region of the first polarity type is formed in the HV well between and in self-alignment with inner edges of the gates. A drift region of the second polarity type is formed in the buffer region between and in self-alignment with inner edges of the gates. The drift region includes a region having a gradual dopant concentration change, and includes a drain region of the second polarity type.
    Type: Application
    Filed: September 16, 2004
    Publication date: March 16, 2006
    Inventors: Jun Cai, Michael Harley-Stead, Jim Holt
  • Publication number: 20060011985
    Abstract: An asymmetric heterodoped metal oxide (AH2MOS) semiconductor device includes a substrate and an insulated gate on the top of the substrate disposed between a source region and a drain region. On one side of the gate, heterodoped tub and source regions are formed. The tub region has dopants of a second polarity. A source region is disposed inside each tub region and has dopants of a first polarity opposite to the second polarity. On the other side of the gate, heterodoped buffer and drift regions are formed. The buffer regions comprise dopants of the second polarity. The drift regions are disposed inside the buffer regions and are doped with dopants of the first polarity. A drain n+ tap region is disposed in the drift region.
    Type: Application
    Filed: July 15, 2004
    Publication date: January 19, 2006
    Inventors: Jun Cai, Michael Harley-Stead, Jim Holt