Abstract: A touch panel assembly structure includes a touch sensor substrate, a cover lens, a sealing frame, and a plurality of transparent elastic elements. The cover lens is facing the touch sensor substrate. The surface of the touch sensor substrate having a sensing region, and the sealing frame is disposed on the surface of the touch sensor substrate and surrounding the sensing region. The sealing frame includes a sealing colloid and a plurality of spacers mixed into the sealing colloid. The cover lens is attached to the touch sensor substrate by the sealing frame such that a gap is formed between the touch sensor substrate and the cover lens. The transparent elastic elements are disposed in the gap and arranged within the sensing region.

Abstract: A transparent touch panel includes a transparent substrate and a transparent layer disposed on the transparent substrate. The surface of the transparent substrate has an electrode region and a wiring region. The transparent layer includes at least one touch sensitive electrode and at least one conductive wiring. The at least one touch sensitive electrode is disposed in the electrode region and has a plurality of bent slits. The at least one conductive wiring is disposed in the wiring region and electrically connected to the touch sensitive electrode and has a bent shape.

Abstract: The present disclosure provides a capacitive touch panel which includes a substrate, M driving electrodes and M×N sensing electrodes, wherein M driving electrodes and M×N sensing electrodes are formed on the substrate. The M driving electrodes are placed parallel to a first axis and are electrically isolated from each other. Each of the M driving electrodes has N sensing electrode regions defined thereon along a second axis, wherein each sensing electrode region has a sensing electrode disposed therein. Each sensing electrode electrically isolated from the driving electrode. The sensing electrode and the corresponding driving electrode generate mutual capacitance. The area associated with each driving electrode is larger than the overall area of the each corresponding sensing electrode.

Abstract: A single-layer capacitive touch-control panel apparatus is provided. The single-layer capacitive touch-control panel apparatus includes a touch-control substrate and a touch-control chip. The touch-control substrate has M touch areas, and each touch area of the plurality of the touch areas includes an axial body and N electrodes. The axial body is electrically connected to the touch-control chip through a first conductive line. N electrodes are disposed on the axial body and are electrically connected to the touch-control chip through a plurality of second conductive lines. The touch-control chip is disposed on the touch-control substrate of single-layer, wherein MN are positive integer.

Abstract: A capacitive touch-control panel apparatus is illustrated. The capacitive touch-control panel apparatus includes a touch-control substrate and a hub circuit. The touch-control substrate has M touch areas, and each touch-control area includes an axial body and N electrodes. N electrodes are disposed corresponding to the axial body and are electrically connected to the hub circuit. One of the electrodes on each touch-control area is connected to one of the electrodes on the other touch-control area by one-to-one manner, wherein M and N are positive integer.

Abstract: A distributed shared memory multi-processor system includes a System Control Unit (SCU) which is made up of a system control unit address section (SCUA) and system control unit data sections (SCUDs). The SCU is scalable by dividing the control and data flow functions of the SCU, and then parallelizing the data path. This allows the number of processors in the system to be increased or higher performance processors to be added by increasing the number of SCUDs and reprogramming crossbar switches incorporated in the SCUA and SCUDs. This results in the overall increase of the multi-processor system performance.

Abstract: A network of integrated communication switches and coherence controllers is provided which interconnected nodes in a cache-coherent multi-processor computer architecture. The nodes contain multiple processors operatively connected to associated memory units through memory controllers. The communication switches and coherence controllers has associated coherence directories which maintain coherence information for all memory lines that are “homed” in the nodes that are directly connected to the particular communication switch and coherence controller.