Patents by Inventor Jim Huang

Jim Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230299756
    Abstract: A latch circuit includes first and second supply nodes having a first voltage value and a second voltage below the first voltage value, first and second input nodes, first and second output nodes, a first switch coupled between the first and second output nodes and turned on and off responsive to first and second clock signal states, first and second transistors coupled between the respective second and first output nodes and the second supply node. A second switch is coupled between a first transistor gate and the first input node, a third switch is coupled between a second transistor gate and the second input node, and each is turned on and off responsive to the first and second states. During the first state, one of the first or second transistors is part of a low resistance path from the first power supply node to the second power supply node.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN, Tien-Chun YANG
  • Patent number: 11677388
    Abstract: A latch circuit includes a power supply node, first and second input nodes, and first and second output nodes. A first switching device is coupled between the first and second output nodes and is turned on and off in response to respective first and second states of a clock signal. A first transistor has a source coupled with a common node, a drain coupled with the second output node, and a gate directly coupled with the first input node, and a second transistor has a source coupled with the common node, a drain coupled with the first output node, and a gate directly coupled with the second input node. A second switching device is coupled between the common node and the power supply node and is turned on and off in response to the respective second and first states of the clock signal.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching (Jim) Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Tien-Chun Yang
  • Patent number: 11049133
    Abstract: Systems, methods, and computer-readable media are disclosed for automated server-based content delivery. In one embodiment, an example method may include determining campaign information for a content delivery campaign, the campaign information comprising a first allocation value for first content, and a second allocation value for second content, determining first observed data comprising a first user response rate for the first content and a second user response rate for the second content, determining an exponentiated gradient algorithm for the content delivery campaign, and determining a reallocation amount to reallocate a portion of the first allocation value to the second allocation value using the exponentiated gradient algorithm based at least in part on the first observed data, wherein the reallocation amount maximizes an output of the exponentiated gradient algorithm.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: June 29, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Jim Huang, Weam Abu Zaki, Cody Barnhart, Teresa Chen, Paula Marie Despins, Yu Gan, Kelly Paulson, Kyle Tiffany, Fabian Lutz-Frank Wauthier
  • Patent number: 10915929
    Abstract: Systems, methods, and computer-readable media are disclosed for detecting user interactions and delivering content using interaction metrics. In one embodiment, an example method may include receiving a bid request for an available content delivery slot, the bid request comprising context information, determining first candidate content for the available content delivery slot, and determining a first base bid value for the first candidate content. Example methods may include determining a predicted conversion rate for an impression of the first candidate content served at the available content delivery slot, determining an estimated revenue for serving the impression at the available content delivery slot, determining a first bid modifier using the predicted conversion rate and the estimated revenue, and sending a response to the bid request comprising a first bid amount, wherein the first bid amount is based at least in part on the first base bid value and the first bid modifier.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: February 9, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Jim Huang
  • Patent number: 10909579
    Abstract: Systems, methods, and computer-readable media are disclosed for detecting viewability and delivering content using viewability metrics. In one embodiment, an example method may include receiving a bid request for an available content delivery slot, where the bid request comprises context information, determining first candidate content for the available content delivery slot, and determining a first base bid value for the first candidate content. Example methods may include determining an estimated view rate using the context information, determining a first bid modifier using the estimated view rate; and sending a response to the bid request comprising a first bid amount. The first bid amount may be based at least in part on the first base bid value and the first bid modifier.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: February 2, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Jim Huang
  • Patent number: 10853735
    Abstract: Systems, methods, and computer-readable media are disclosed for maximizing quantifiable user interaction via modification of adjustable parameters. In one embodiment, an example method may include determining a first output to maximize, where the first output is a function of a first adjustable parameter and a second adjustable parameter, determining first data comprising a first actual value of the first output when the first adjustable parameter is set to a first value and the second adjustable parameter is set to a second value, and determining a first predictive model that generates a first predicted value of the first output. Example methods may include determining, using the first predictive model, a third value for the first adjustable parameter and a fourth value for the second adjustable parameter to maximize the first predicted value, and sending the third value and the fourth value.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: December 1, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Yu Gan, Cédric Philippe Archambeau, Rodolphe Jenatton, Jim Huang, Fabian Lutz-Frank Wauthier
  • Patent number: 10651942
    Abstract: One example includes a bias-based Mach-Zehnder modulation (MZM) system. The system includes a Mach-Zehnder modulator to receive and split an optical input signal and to provide an intensity-modulated optical output signal based on a high-frequency data signal to modulate a relative phase of the split optical input signal to transmit data and based on a bias voltage to modulate the relative phase of the split optical input signal to tune the Mach-Zehnder modulator. The system also includes a bias feedback controller to compare a detection voltage associated with the intensity-modulated output signal with a reference voltage to measure an extinction ratio associated with an optical power of the intensity-modulated optical output signal and to adjust the bias voltage based on the comparison to substantially maximize the extinction ratio.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: May 12, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Cheng Li, Jim Huang, Ashkan Seyedi, Marco Fiorentino, Raymond G. Beausoleil
  • Patent number: 10565622
    Abstract: Systems, methods, and computer-readable media are disclosed for optimization of real-time probabilistic model evaluation for online advertising. In one embodiment, a system may receive a bid request for an ad slot, and may receive cached user information with a first ad and a first ad score, and a second ad and a second ad score. The system may generate a first estimated probability of conversion associated with presentation of the first ad to the user, and may generate a second estimated probability of conversion associated with presentation of the second ad to the user based at least in part on the context information, the second ad identifier, and the second ad score. The system may select either the first ad or the second ad for which to generate a bid amount based at least in part on the first estimated probability of conversion and the second estimated probability of conversion.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: February 18, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Jonathan Lee Burstein, Jim Huang
  • Patent number: 10536146
    Abstract: An edge detector includes an output node selectively coupled to a first voltage node through a first transistor, the first voltage node having a first voltage level, and a second transistor configured to continuously couple the output node to a second voltage node having a second voltage level. A capacitor includes a first terminal coupled to a gate of the first transistor and a second terminal configured to receive an input signal.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching (Jim) Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin
  • Publication number: 20190273500
    Abstract: An edge detector includes an output node selectively coupled to a first voltage node through a first transistor, the first voltage node having a first voltage level, and a second transistor configured to continuously couple the output node to a second voltage node having a second voltage level. A capacitor includes a first terminal coupled to a gate of the first transistor and a second terminal configured to receive an input signal.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 5, 2019
    Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN
  • Patent number: 10367491
    Abstract: A delay line circuit including: a coarse-tuning arrangement, including delay units, the coarse-tuning arrangement being configured to coarsely-tune an input signal by transferring the input signal through a selected number of the delay units and thereby producing a first output signal; and a fine-tuning arrangement configured to receive the first output signal at a beginning of a signal path which includes at least three serially-connected inverters, finely-tune the first output signal along the signal path, and produce a second output signal at an end of the signal path; the fine-tuning arrangement including: a speed control unit which is selectively-connectable, and a switching circuit to selectively connect the speed control unit to the signal path based on a process-corner signal.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tsung-Ching (Jim) Huang, Chih-Chang Lin, Tien-Chun Yang
  • Publication number: 20190190610
    Abstract: One example includes a bias-based Mach-Zehnder modulation (MZM) system. The system includes a Mach-Zehnder modulator to receive and split an optical input signal and to provide an intensity-modulated optical output signal based on a high-frequency data signal to modulate a relative phase of the split optical input signal to transmit data and based on a bias voltage to modulate the relative phase of the split optical input signal to tune the Mach-Zehnder modulator. The system also includes a bias feedback controller to compare a detection voltage associated with the intensity-modulated output signal with a reference voltage to measure an extinction ratio associated with an optical power of the intensity-modulated optical output signal and to adjust the bias voltage based on the comparison to substantially maximize the extinction ratio.
    Type: Application
    Filed: February 14, 2019
    Publication date: June 20, 2019
    Inventors: Cheng Li, Jim Huang, Ashkan Seyedi, Marco Fiorentino, Raymond G. Beausoleil
  • Patent number: 10298237
    Abstract: A level shifting apparatus includes a first inverter configured to receive an input signal and a second inverter capacitively coupled with an output of the first inverter, the second inverter being configured to output an output signal. A transmission gate is configured to feed back the output signal to an input of the second inverter, wherein the transmission gate is configured to selectively interrupt feedback of the output signal to the input of the second inverter.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching (Jim) Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin
  • Patent number: 10243662
    Abstract: One example includes a bias-based Mach-Zehnder modulation (MZM) system. The system includes a Mach-Zehnder modulator to receive and split an optical input signal and to provide an intensity-modulated optical output signal based on a high-frequency data signal to modulate a relative phase of the split optical input signal to transmit data and based on a bias voltage to modulate the relative phase of the split optical input signal to tune the Mach-Zehnder modulator. The system also includes a bias feedback controller to compare a detection voltage associated with the intensity-modulated output signal with a reference voltage to measure an extinction ratio associated with an optical power of the intensity-modulated optical output signal and to adjust the bias voltage based on the comparison to substantially maximize the extinction ratio.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: March 26, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Cheng Li, Jim Huang, Ashkan Seyedi, Marco Fiorentino, Raymond G Beausoleil
  • Publication number: 20180294803
    Abstract: A delay line circuit including: a coarse-tuning arrangement, including delay units, the coarse-tuning arrangement being configured to coarsely-tune an input signal by transferring the input signal through a selected number of the delay units and thereby producing a first output signal; and a fine-tuning arrangement configured to receive the first output signal at a beginning of a signal path which includes at least three serially-connected inverters, finely-tune the first output signal along the signal path, and produce a second output signal at an end of the signal path; the fine-tuning arrangement including: a speed control unit which is selectively-connectable, and a switching circuit to selectively connect the speed control unit to the signal path based on a process-corner signal.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tsung-Ching (Jim) HUANG, Chih-Chang LIN, Tien-Chun YANG
  • Publication number: 20180241380
    Abstract: A latch circuit includes a power supply node, first and second input nodes, and first and second output nodes. A first switching device is coupled between the first and second output nodes and is turned on and off in response to respective first and second states of a clock signal. A first transistor has a source coupled with a common node, a drain coupled with the second output node, and a gate directly coupled with the first input node, and a second transistor has a source coupled with the common node, a drain coupled with the first output node, and a gate directly coupled with the second input node. A second switching device is coupled between the common node and the power supply node and is turned on and off in response to the respective second and first states of the clock signal.
    Type: Application
    Filed: April 24, 2018
    Publication date: August 23, 2018
    Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN, Tien-Chun YANG
  • Patent number: 9998103
    Abstract: A delay line circuit includes: a coarse-tuning arrangement, including delay units; and a fine-tuning arrangement including at least three serially-connected inverters. The coarse-tuning arrangement is configured to receive an input signal and coarsely-tune the input signal, the coarsely-tuning including transferring the input signal through a selected number of the delay units and thereby producing a first output signal. The fine-tuning arrangement is configured to receive the first output signal, finely-tune the first output signal, and produce a second output signal, the finely-tuning including selectively connecting a speed control unit to a node between a corresponding pair of the at least three serially-connected inverters.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tsung-Ching (Jim) Huang, Chih-Chang Lin, Tien-Chun Yang
  • Publication number: 20180138909
    Abstract: A level shifting apparatus includes a first inverter configured to receive an input signal and a second inverter capacitively coupled with an output of the first inverter, the second inverter being configured to output an output signal. A transmission gate is configured to feed back the output signal to an input of the second inverter, wherein the transmission gate is configured to selectively interrupt feedback of the output signal to the input of the second inverter.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 17, 2018
    Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN
  • Patent number: 9966935
    Abstract: A latch circuit includes a first input node, a second input node, a first output node, a second output node, a first switching device coupled between the first output node and the second output node, and a first amplification circuit coupled with the first input node, the second input node, the first output node, and the second output node. The first switching device is configured to be turned on in response to a first state of a clock signal and to be turned off in response to a second state of the clock signal. The first amplification circuit is configured to cause a voltage difference across the first switching device based on voltage levels of the first input node and the second input node in response to the first state of the clock signal.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: May 8, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching (Jim) Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Tien-Chun Yang
  • Publication number: 20180109322
    Abstract: One example includes a bias-based Mach-Zehnder modulation (MZM) system. The system includes a Mach-Zehnder modulator to receive and split an optical input signal and to provide an intensity-modulated optical output signal based on a high-frequency data signal to modulate a relative phase of the split optical input signal to transmit data and based on a bias voltage to modulate the relative phase of the split optical input signal to tune the Mach-Zehnder modulator. The system also includes a bias feedback controller to compare a detection voltage associated with the intensity-modulated output signal with a reference voltage to measure an extinction ratio associated with an optical power of the intensity-modulated optical output signal and to adjust the bias voltage based on the comparison to substantially maximize the extinction ratio.
    Type: Application
    Filed: May 27, 2015
    Publication date: April 19, 2018
    Inventors: Cheng Li, Jim Huang, Ashkan Seyedi, Marco Fiorentino, Raymond G Beausoleil