Abstract: A multi-layered structure, and method for producing same, which may include at least one glass layer anodically bonded to an intermediate layer. The intermediate layer may function as an anodic bonding layer, an etch stop layer, and/or a hard mask layer. A template may be formed of the multi-layered structure by forming a desired pattern of openings therein by way of, for example, etching. Such a template may, for example, be used in the alignment and adherence of spacer structures to an electrode plate during the fabrication of flat panel displays. When used in this context, the construction of such a template results in more precise control of the patterning and sizing of the holes formed therein which thereby allows for more precise placement of spacer structures as well as the use of spacer structures exhibiting relatively higher aspect ratios during the fabrication of flat panel displays.

Abstract: A method for cleansing the phosphor screen of a display device comprising the removal of oxygen or sulfur from the surface of the phosphor, and/or its associated binder material, to a depth that prevents oxygen diffusion from the phosphor and/or binder, thereby creating an oxygen deficient surface on the phosphors.

Abstract: A multi-layered structure, and method for producing same, which may include at least one glass layer anodically bonded to an intermediate layer. The intermediate layer may function as an anodic bonding layer, an etch stop layer, and/or a hard mask layer. A template may be formed of the multi-layered structure by forming a desired pattern of openings therein by way of, for example, etching. Such a template may, for example, be used in the alignment and adherence of spacer structures to an electrode plate during the fabrication of flat panel displays. When used in this context, the construction of such a template results in more precise control of the patterning and sizing of the holes formed therein which thereby allows for more precise placement of spacer structures as well as the use of spacer structures exhibiting relatively higher aspect ratios during the fabrication of flat panel displays.

Abstract: A multi-layered structure, and method for producing same, which may include at least one glass layer anodically bonded to an intermediate layer. The intermediate layer may function as a anodic bonding layer, an etch stop layer, and/or a hard mask layer. A template may be formed of the multi-layered structure by forming a desired pattern of openings therein by way of, for example, etching. Such a template may, for example, be used in the alignment and adherence of spacer structures to an electrode plate during the fabrication of flat panel displays. When used in this context, the construction of such a template results in more precise control of the patterning and sizing of the holes formed therein which thereby allows for more precise placement of spacer structures as well as the use of spacer structures exhibiting relatively higher aspect ratios during the fabrication of flat panel displays.

Abstract: A method for cleansing the phosphor screen of a display device comprising the removal of oxygen or sulfur from the surface of the phosphor, and/or its associated binder material, to a depth that prevents oxygen diffusion from the phosphor and/or binder, thereby creating an oxygen deficient surface on the phosphors.

Abstract: A method for cleansing the phosphor screen of a display device comprising the removal of oxygen or sulfur from the surface of the phosphor, and/or its associated binder material, to a depth that prevents oxygen diffusion from the phosphor and/or binder, thereby creating an oxygen deficient surface on the phosphors.

Abstract: The present invention discloses a method for accurately maintaining an alignment of a faceplate and a cathode member during the manufacturing of field emission displays and plasma displays. The invention maintains the alignment in preparation for, and throughout, the sealing process of these displays through the application of a glass frit material on at least one of the plates. A sol-gel material is further applied on top of the glass frit; and, in addition, for optimum performance, an adhesive material is used in conjunction with the sol-gel material for enhanced support of the plates during the early stages of the sealing process. The adhesive material, which maintains the alignment early in the sealing process, may evaporate or soften as the temperature increases, at which point, the sol-gel material maintains the plates in alignment during the softening of the seal frit.

Abstract: According to the invention, a process is provided for controlling illumination of a pixel in a field emission display. In one embodiment, the process includes the steps of providing a first voltage to the first tip array, providing a second voltage to the second tip array in which the second voltage is different than the first voltage. In another embodiment of the invention, a field emission display is provided which has a plurality of pixels, each pixel having at least a first tip array and a second tip array, a column conductor, or electrode, an electrical communication with the first tip array.

Abstract: The present invention teaches a field emission display ("FED") architecture for isolating display grids, wherein an FED has a plurality of pixels. Each of the pixels comprise at least two field emitter tips for displaying information to the pixel and a pixelator for driving the field emitter tips. Further, an isolated display grid is incorporated for each of the field emitter tips. Each display grids is coupled to a bus having a predetermined voltage by a link. In one embodiment of the present invention, the link can be disintegrated by internal or external means. In a second embodiment, the FED comprises a first and second bus, each of bus having a predetermined voltage, whereby a first isolated display grid is coupled to the first bus by a first link and a second isolated display grids is coupled to the second bus by a second link.

Abstract: The present invention teaches a field emission display ("FED") architecture for isolating display grids, wherein an FED has a plurality of pixels. Each of the pixels comprise at least two field emitter tips for displaying information to the pixel and a pixelator for driving the field emitter tips. Further, an isolated display grid is incorporated for each of the field emitter tips. Each display grids is coupled to a bus having a predetermined voltage by a link. In one embodiment of the present invention, the link can be disintegrated by internal or external means. In a second embodiment, the FED comprises a first and second bus, each of bus having a predetermined voltage, whereby a first isolated display grid is coupled to the first bus by a first link and a second isolated display grids is coupled to the second bus by a second link.

Abstract: A Field Emission Display ("FED") is disclosed having a brightness to project images. To achieve this benefit, the FED comprises a pixelator is coupled to a display for displaying and projecting the image. By design, the pixelator conducts a current, corresponding to a degree of brightness in the resulting panel display, through the display grid. A first resistor having a first value, is coupled between the pixelator and a voltage node or ground. Moreover, a second resistor having a second value comprising at most one half of the first value is employed. A switch for connecting the first resistor in parallel with the second resistor is utilized such that when a control signal is received, the switch is enabled and the equivalent resistance between the pixelator and a voltage node or ground is substantially reduced.

Abstract: A Field Emission Display ("FED") is disclosed having a brightness to project images. To achieve this benefit, the FED includes a pixelator is coupled to a display for displaying and projecting the image. By design, the pixelator conducts a drive current passing through the display grid corresponding to a degree of brightness in the resulting panel display. A first resistor having a first value is coupled between the pixelator and a voltage node or ground. Moreover, a second resistor having a second value at most one half of the first value is employed. A switch for connecting the first resistor in parallel with the second resistor is closed when a control signal is received. When the switch is enabled, the equivalent resistance between the pixelator and a voltage node or ground is substantially reduced. In another embodiment, a tapped resistor replaces the first resistor and the second resistor. When the control signal is received, a portion of the drive current is shunted through the switch.

Abstract: The present invention teaches a field emission display ("FED") architecture for isolating display grids, wherein an FED has a plurality of pixels. Each of the pixels comprise at least two field emitter tips for displaying information to the pixel and a pixelator for driving the field emitter tips. Further, an isolated display grid is incorporated for each of the field emitter tips. Each display grid is coupled by a link to a bus having a predetermined voltage. In one embodiment of the present invention, the link can be disintegrated by internal or external means. In a second embodiment, the FED comprises a first and second bus, each bus having a predetermined voltage, whereby a first isolated display grid is coupled to the first bus by a first link and a second isolated display grids is coupled to the second bus by a second link.

Abstract: A Field Emission Display ("FED") is disclosed having a brightness to project images. To achieve this benefit, the FED includes a pixelator which coupled to a display for displaying and projecting the image. By design, the pixelator conducts a drive current passing through the display grid corresponding to a degree of brightness in the resulting panel display. A first resistor having a first value is coupled between the pixelator and a voltage node or ground. Moreover, a second resistor having a second value at most one half of the first value is employed. A switch for connecting the first resistor in parallel with the second resistor is closed when a control signal is received when the switch is enabled, the equivalent resistance between the pixelator and a voltage node or ground is substantially reduced. In another embodiment, a tapped resistor replaces the first resistor and the second resistor. When the control signal is received, a portion of the drive current is shunted through the switch.