Abstract: A fault tolerant bus architecture and protocol for use in applications wherein data must be handled with a high degree of integrity and in a fault tolerant manner. As applied to an integrated flight hazard avoidance system, the system is constructed of two or more microprocessor-driven modules that generate data, two independent bus interface controllers per module, and an inter-module backplane data bus that links each module. The system allows comparison of identical data from multiple sources. If invalid data is detected, the system either passes the correct data copy or generates a system fault message. The bus architecture utilizes a distributed synchronization protocol, and does not require a master synchronization source.