Patents by Inventor Jim Nobugaki

Jim Nobugaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Delayed FIFO status for serial shift emulation
    Patent number: 5619681
    Abstract: Delay circuitry is used in a circuit to delay the transmission of groups of data until another circuit expects these groups of data. In one embodiment, emulating circuitry is used to emulate the timing of transmitter and receiver UART FIFOs. This emulating circuitry uses delays equal to the amount of time the UART FIFOs take to serially shift out data in the transmitter UART FIFO, and to serially shift in data in the receiver UART FIFO. This allows the modem chip to use a parallel-to-parallel FIFO buffer for the transmitter FIFO buffer and the receiver FIFO buffer.
    Type: Grant
    Filed: June 30, 1993
    Date of Patent: April 8, 1997
    Assignee: Zilog, Inc.
    Inventors: Boubekeur Benhamida, Grant Richards, Stephen H. Chan, Gyle Yearsley, Jim Nobugaki