Patents by Inventor Jim Shih-Chun Liang

Jim Shih-Chun Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10347529
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to interconnect structures and methods of manufacture. The structure includes a metallization feature comprising a fill material and formed within a dielectric layer; at least one cap covering the fill material of the metallization feature, the at least one cap is comprised of a material different than the fill material of the metallization feature; and an interconnect structure in electrical contact with the metallization feature.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jim Shih-Chun Liang, Keith Kwong Hon Wong
  • Publication number: 20190181044
    Abstract: A contact element structure of a semiconductor device includes an opening positioned in an insulating material layer, the insulating material layer being positioned above a semiconductor substrate, and the opening having an upper sidewall portion, a lower sidewall portion, and a bottom surface portion. An insulating liner portion is positioned within the opening, the insulating liner portion covering the insulating material layer at the upper sidewall portion but not covering the insulating material layer at the lower sidewall portion. A contact liner is positioned within the opening and covers the insulating liner portion, the insulating material layer at the lower sidewall portion, and the insulating material layer at the bottom surface portion, and a conductive material is positioned in the opening and covers the contact liner.
    Type: Application
    Filed: February 19, 2019
    Publication date: June 13, 2019
    Inventor: Jim Shih-Chun Liang
  • Publication number: 20190103310
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to interconnect structures and methods of manufacture. The structure includes a metallization feature comprising a fill material and formed within a dielectric layer; at least one cap covering the fill material of the metallization feature, the at least one cap is comprised of a material different than the fill material of the metallization feature; and an interconnect structure in electrical contact with the metallization feature.
    Type: Application
    Filed: October 4, 2017
    Publication date: April 4, 2019
    Inventors: Jim Shih-Chun LIANG, Keith Kwong Hon Wong
  • Patent number: 10249534
    Abstract: The present disclosure provides a contact element of a semiconductor device structure, wherein an opening is formed in an insulating material layer, the insulating material layer being provided over a semiconductor substrate. Within a lower portion of the opening, a contact liner portion is formed, the contact liner portion covering a bottom of the opening and partially covering a lower sidewall portion of the lower portion of the opening such that an upper sidewall portion at an upper portion of the opening is exposed to further processing. An insulating liner portion is formed within the opening, the insulating liner portion covering the exposed upper sidewall portion. Furthermore, a contact liner is formed within the opening, the contact liner covering the contact liner portion in the insulating liner portion, and the opening is filled with a conductive material.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Jim Shih-Chun Liang
  • Publication number: 20180350679
    Abstract: The present disclosure provides a contact element of a semiconductor device structure, wherein an opening is formed in an insulating material layer, the insulating material layer being provided over a semiconductor substrate. Within a lower portion of the opening, a contact liner portion is formed, the contact liner portion covering a bottom of the opening and partially covering a lower sidewall portion of the lower portion of the opening such that an upper sidewall portion at an upper portion of the opening is exposed to further processing. An insulating liner portion is formed within the opening, the insulating liner portion covering the exposed upper sidewall portion. Furthermore, a contact liner is formed within the opening, the contact liner covering the contact liner portion in the insulating liner portion, and the opening is filled with a conductive material.
    Type: Application
    Filed: May 30, 2017
    Publication date: December 6, 2018
    Inventor: Jim Shih-Chun Liang
  • Publication number: 20180166385
    Abstract: Aspects of the present disclosure include a method for forming a contact on a semiconductor device, the semiconductor device including a conductive region disposed over a substrate, the method comprising: depositing a dielectric material on the substrate; forming an opening in the dielectric material to expose the conductive region; forming a barrier layer on a lower surface and sidewalls of the opening in the dielectric material, the barrier layer terminating below an upper surface of the dielectric material and surrounding a lower portion of the opening; depositing cobalt in the lower portion of the opening, the cobalt terminating at an upper surface of the barrier layer; depositing tungsten to fill the opening to at least the upper surface of the dielectric material; and planarizing the upper surface of the dielectric material with the tungsten in the opening.
    Type: Application
    Filed: February 9, 2018
    Publication date: June 14, 2018
    Inventors: Jim Shih-Chun Liang, Keith Kwong Hon Wong
  • Publication number: 20180138123
    Abstract: Aspects of the present disclosure include a semiconductor device which includes a dielectric layer deposited over a conductive region and an interconnect electrically connecting the conductive region with a top surface of the dielectric layer. The interconnect includes a barrier layer extending from an interior of the dielectric layer to the conductive region and covering the conductive region. The barrier layer encases a cobalt plug. The interconnect includes a tungsten cap on an upper surface of the cobalt plug. The tungsten cap is coplanar with an upper surface of the dielectric layer. A method of manufacturing the semiconductor device is also provided.
    Type: Application
    Filed: November 15, 2016
    Publication date: May 17, 2018
    Inventors: Jim Shih-Chun Liang, Keith Kwong Hon Wong
  • Publication number: 20180096933
    Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 5, 2018
    Inventors: Jim Shih-Chun Liang, Atsushi Ogino, Justin C. Long
  • Patent number: 9793216
    Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Joyeeta Nag, Jim Shih-Chun Liang, Domingo A. Ferrer Luppi, Atsushi Ogino, Andrew H. Simon, Michael P. Chudzik
  • Publication number: 20170213792
    Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.
    Type: Application
    Filed: January 26, 2016
    Publication date: July 27, 2017
    Inventors: Joyeeta Nag, Jim Shih-Chun Liang, Domingo A. Ferrer Luppi, Atsushi Ogino, Andrew H. Simon, Michael P. Chudzik
  • Patent number: 9633946
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to seamless metallization structures and methods of manufacture. A structure includes: a contact opening formed in an oxide material and in alignment with an underlying structure; a metal liner lining the sidewalls and bottom of the contact opening, in direct electrical contact with the underlying structure; a conductive liner on the metal liner, within the contact opening; and tungsten fill material on the conductive liner and within the contact opening.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jim Shih-Chun Liang, Domingo A. Ferrer, Kathryn T. Schonenberg, Shahrukh Akbar Khan, Wei-Tsu Tseng
  • Patent number: 9293365
    Abstract: The present invention relates generally to forming interconnects over contacts and more particularly, to a method and structure for filling interconnect trenches with a sacrificial filler material before removal of a hard mask layer to protect the liners of the contacts from damage during the removal process. A method is disclosed that may include: filling an opening in a dielectric layer above a contact and a contact liner with a sacrificial filler material, such that the contact liner is completely covered by the sacrificial filler material; removing a hard mask layer used to pattern and form the opening; and removing the sacrificial filler material from the opening selective to the dielectric layer, the contact liner, and the contact to form an interconnect trench.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Domingo A. Ferrer, Jim Shih-Chun Liang, Joyeeta Nag, Wei-tsu Tseng, George S. Tulevski
  • Publication number: 20150279733
    Abstract: The present invention relates generally to forming interconnects over contacts and more particularly, to a method and structure for filling interconnect trenches with a sacrificial filler material before removal of a hard mask layer to protect the liners of the contacts from damage during the removal process. A method is disclosed that may include: filling an opening in a dielectric layer above a contact and a contact liner with a sacrificial filler material, such that the contact liner is completely covered by the sacrificial filler material; removing a hard mask layer used to pattern and form the opening; and removing the sacrificial filler material from the opening selective to the dielectric layer, the contact liner, and the contact to form an interconnect trench.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Applicant: International Business Machines Corporation
    Inventors: Domingo A. Ferrer, Jim Shih-Chun Liang, Joyeeta Nag, Wei-tsu Tseng, George S. Tulevski