Patents by Inventor Jim Sutherland

Jim Sutherland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5338984
    Abstract: The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical columns of logic cells. The array further includes at least one horizontally aligned express bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned express bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array further includes at least one generally diagonally aligned local and/or express bus running between adjacent diagonally aligned logic cells, the adjacent diagonally aligned logic cells being connectable thereto.
    Type: Grant
    Filed: February 5, 1993
    Date of Patent: August 16, 1994
    Assignee: National Semiconductor Corp.
    Inventor: Jim Sutherland
  • Patent number: 5298805
    Abstract: A low transistor count programmable bussing resource for a programmable logic array allows the use of the bussing resources as inputs or outputs to a cell in the array and allows connections between different buses without effecting the normal use of the cell. The bussing resource allows efficient routing of signals between cells and is symmetric to allow rotation of logic macros built using combinations of cells and buses.
    Type: Grant
    Filed: April 8, 1993
    Date of Patent: March 29, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Tim Garverick, Jim Sutherland, Sanjay Popli, Venkata Alturi, Arthur Smith, Jr., Scott Pickett, David Hawley, Shao-Pin Chen, Shankar Moni, Benjamin S. Ting, Rafael C. Camarota, Shin-Mann Day, Frederick Furtek
  • Patent number: 5296759
    Abstract: The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical columns of logic cells. Adjacent abutting cells logic cells are interconnectable via horizontal and vertical configurable interconnections running between adjacent cells. Furthermore, configurable diagonal interconnections run between diagonally adjacent abutting logic cells in the array.
    Type: Grant
    Filed: June 18, 1993
    Date of Patent: March 22, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Jim Sutherland, Sanjay Popli, Venkata Alturi, Frederick Furtek