Patents by Inventor Jim Wunderlich

Jim Wunderlich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PLL for clock recovery with initialization sequence
    Patent number: 6794945
    Abstract: A phase locked loop circuit is used to provide timing clocks for data bit recovery from a serial data flow. The system locks to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clocking in the individual data bits.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: September 21, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James J. McDonald, II, Ronald B. Hulfachor, Jim Wunderlich
  • PLL for clock recovery with initialization sequence
    Publication number: 20030193374
    Abstract: A phase locked loop circuit is used to provide timing clocks for data bit recovery from a serial data flow. The system locks to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clocking in the individual data bits.
    Type: Application
    Filed: April 11, 2003
    Publication date: October 16, 2003
    Inventors: James J. McDonald, Ronald B. Hulfachor, Jim Wunderlich