Abstract: A method and apparatus for adjusting the charge for a battery under a power sharing arrangement is disclosed. In one embodiment, the method comprises determining if power output capacity of an alternating current (AC) adapter is less than or greater than a system power requirement for a system that receives power from the AC adapter and a battery, determining a charge current for charging the battery from the AC adapter, based on a voltage range of the battery, the current charge being less than excess current available from the AC adapter in view of determining that the power output capacity of the AC adapter is greater than the system power requirement, and controlling a battery charger to charge the battery with the charge current by specifying the charge current to the battery charger if the power output capacity of the AC adapter is greater than the system power requirement.

Abstract: A method and apparatus for adjusting the charge for a battery under a power sharing arrangement is disclosed. In one embodiment, the method comprises determining if power output capacity of an alternating current (AC) adapter is less than or greater than a system power requirement for a system that receives power from the AC adapter and a battery, determining a charge current for charging the battery from the AC adapter, based on a voltage range of the battery, the current charge being less than excess current available from the AC adapter in view of determining that the power output capacity of the AC adapter is greater than the system power requirement, and controlling a battery charger to charge the battery with the charge current by specifying the charge current to the battery charger if the power output capacity of the AC adapter is greater than the system power requirement.

Abstract: Included are embodiments for processing video data. At least one embodiment includes a logic configured to receive video data having a format chosen from at least two formats and logic configured to receive an instruction from an instruction set including an indication of the format of the video data. Some embodiments include first parallel logic configured to process video data according to a first format in response to the indication is the first format and second parallel logic configured to process the video data according to a second format in response to the indication is the second format.

Abstract: Disclosed is a graphics processing unit comprising an instruction decoder and sum-of-absolute-differences (SAD) accleration logic. The instruction decoder is configured to decode a SAD instruction into parameters describing an M×N and an n×n pixel block in U,V coordinates. The SAD accleration logic is configured to receive the parameters and compute SAD scores. Each SAD score corresponds to the n×n block and to one block contained within the M×N pixel block and horizontally offset within the n×n block. Also disclosed is a GPU comprising a host processor interface receiving video acceleration instructions and a video acceleration unit. The unit is responsive to the instructions and comprises SAD accleration logic configured to receive the parameters and compute SAD scores. Each SAD score corresponds to an n×n pixel block and to one block contained within an M×N block and horizontally offset within the n×n block. M, N, and n are integers.

Abstract: Disclosed are systems and methods for debugging and analyzing graphics hardware designs. Hardware designs are represented by a software model implemented in a programming language. Graphics operations can be executed in the software model as well as in reference software models to allow a user to analyze the accuracy of a graphics hardware design and/or a device driver implementation.

Abstract: Systems and methods for graphics data management are described. One embodiment includes a graphics processing system comprising a texture management unit configured to organize texture map data according to a slice major format, wherein the texture map data spans at least one mip level. Furthermore, the graphics processing system comprises a texture cache, wherein the texture cache is coupled to the texture management unit and configured to receive the organized texture map data from the texture management unit.

Abstract: Systems and methods for graphics data management are described. One embodiment includes a method for reducing bank collisions within a level 2 (L2) cache comprising the following: reading texture data from external memory configured to store texture data used for texture filtering within the graphics processing unit, partitioning the texture data into banks, performing a bank swizzle operation on the banks, and writing the banks of data to the L2 cache.

Abstract: Systems and methods for border color handling in a graphics processing unit are disclosed. In one embodiment, the system includes a border color register that stores at least one border color pointer. A border color pointer indicates an address in an external memory at which border color information is located. Border color information is populated within external memory and retrieved by the texture cache controller if the texture filter unit requires a border color for texture mapping operations.

Abstract: Disclosed are systems and methods for debugging and analyzing graphics hardware designs. Hardware designs are represented by a software model implemented in a programming language. Graphics operations can be executed in the software model as well as in reference software models to allow a user to analyze the accuracy of a graphics hardware design and/or a device driver implementation.

Abstract: Systems and methods for graphics data management are described. One embodiment includes a graphics processing system comprising a texture management unit configured to organize texture map data according to a slice major format, wherein the texture map data spans at least one mip level. Furthermore, the graphics processing system comprises a texture cache, wherein the texture cache is coupled to the texture management unit and configured to receive the reorganized texture map data from the texture management unit.

Abstract: Disclosed is a graphics processing unit comprising an instruction decoder and sum-of-absolute-differences (SAD) accleration logic. The instruction decoder is configured to decode a SAD instruction into parameters describing an M×N and an n×n pixel block in U,V coordinates. The SAD accleration logic is configured to receive the parameters and compute SAD scores. Each SAD score corresponds to the n×n block and to one block contained within the M×N pixel block and horizontally offset within the n×n block. Also disclosed is a GPU comprising a host processor interface receiving video acceleration instructions and a video acceleration unit. The unit is responsive to the instructions and comprises SAD accleration logic configured to receive the parameters and compute SAD scores. Each SAD score corresponds to an n×n pixel block and to one block contained within an M×N block and horizontally offset within the n×n block. M, N, and n are integers.

Abstract: Systems and methods for graphics data management are described. One embodiment includes a method for reducing bank collisions within a level 2 (L2) cache comprising the following: reading texture data from external memory configured to store texture data used for texture filtering within the graphics processing unit, partitioning the texture data into banks, performing a bank swizzle operation on the banks, and writing the banks of data to the L2 cache.

Abstract: Included are embodiments for processing video data. At least one embodiment includes a logic configured to receive video data having a format chosen from at least two formats and logic configured to receive an instruction from an instruction set including an indication of the format of the video data. Some embodiments include first parallel logic configured to process video data according to a first format in response to the indication is the first format and second parallel logic configured to process the video data according to a second format in response to the indication is the second format.

Abstract: Systems and methods for border color handling in a graphics processing unit are disclosed. In one embodiment, the system includes a border color register that stores at least one border color pointer. A border color pointer indicates an address in an external memory at which border color information is located. Border color information is populated within external memory and retrieved by the texture cache controller if the texture filter unit requires a border color for texture mapping operations.

Abstract: Tantalum barrier layer chemical mechanical polishing may be improved by using suitably aged slurries. Slurries that are older than fifty days from their manufacture date result in significantly lower occurrences of defects.

Abstract: A rocking crib or cradle having a motion inducing mechanism with automatic lock. The motion inducing mechanism imparts a movement to a movable portion of the crib or cradle in relation to a longitudinal base while the lock immobilizes the movable portion in relation to the base. Operation of both the motion inducing mechanism and lock are related to one another with a timer such that the lock automatically immobilizes the movable portion of the crib when the time duration of the motion inducing mechanism is expended. A time delay switch may be connected between the timer and lock to delay operation of the lock for a preset time after the expiration of the time duration of the motion inducing mechanism. A handle may be connected to the lock to manually operate the lock to immobilize or free the movable portion of the crib in relation to the longitudinal base, such manual operation energizing or de-energizing the timer and motion inducing device accordingly.

Abstract: A cradle assembly having a stationary base, a rocking crib, a rocking motion inducing mechanism, and a crib motion lock. The motion inducing mechanism imparts a rocking movement to the rocking crib in relation to the base while the lock functions to immobilize the rocking crib relative to the base. Operation of both the motion inducing mechanism and lock are preferably related to one another so that the lock automatically immobilizes the rocking crib upon expiration of a previously selected time duration for operation of the motion inducing mechanism. A time delay switch or a microprocessor may be connected to delay operation of the lock for a preset time after the expiration of the selected time duration. The controls may include, for example, buttons for actuating or deactuating rocking motion, or a handle connected to the lock device to manually actuate or deactivate the lock device to free the rocking crib for rocking movement relative to the base.

Abstract: A rocking crib or cradle having a motion inducing mechanism with automatic lock. The motion inducing mechanism imparts a movement to a movable portion of the crib or cradle in relation to a longitudinal base while the lock immobilizes the movable portion in relation to the base. Operation of both the motion inducing mechanism and lock are related to one another with a timer such that the lock automatically immobilizes the movable portion of the crib when the time duration of the motion inducing mechanism is expended. A time delay switch may be connected between the timer and lock to delay operation of the lock for a preset time after the expiration of the time duration of the motion inducing mechanism. A handle may be connected to the lock to manually operate the lock to immobilize or free the movable portion of the crib in relation to the longitudinal base, such manual operation energizing or de-energizing the timer and motion inducing device accordingly.

Abstract: A method and system for improving overall system capacity in GSM networks by reducing the number of home location register and visitor location register queries is disclosed. The method and system allows the reuse of the MSRN by allocating the MSRN to a mobile terminal and using it for future calls. The method of the present invention allows the GMSC to cache the MSRN for a called mobile terminal. During a first call setup, an entry is recorded at a cache register that maps the Mobile Subscriber ISDN Number (MSISDN) of the mobile terminal to a previously allocated MSRN. Additionally, the Bearer Capability (BC) associated with this MSRN is also recorded in the cache register. When the next call arrives, the GMSC first checks if a MSRN for that called mobile terminal already exists in its cache register. If a cached MSRN is available and the BC associated with the cached MSRN matches the BC requested by the current call, then the GMSC uses the cached MSRN to route the call to the VMSC.

Abstract: A method is illustrated for reducing the call setup time of high priority calls such as voice or high speed user generated data without unduly wasting RF frequency resources on non priority calls such as short message calls. This is accomplished by ascertaining the call priority at the base station controller (BSC) level in a GSM system soon after call initiation and immediately changing the channel assignment for use by the remaining signalling type messages to a different operational speed where appropriate. The concept is further extended by supplying the call priority data to a called party's BSC such that all signalling messages after initial contact can be at the operational speed appropriate to the priority of the call.