Abstract: Embodiments described herein provide methods and apparatus used to reduce or substantially eliminate undesirable scratches to the non-active surface of a substrate by monitoring and controlling the deflection of a substrate, and thus the contact force between the substrate and a substrate support, during substrate processing. In one embodiment a method for processing a substrate includes positioning the substrate on a patterned surface of a substrate support, where the substrate support is disposed in a processing volume of a processing chamber, applying a chucking voltage to a chucking electrode disposed in the substrate support; flowing a gas into a backside volume disposed between the substrate and the substrate support, monitoring a deflection of the substrate, and changing a chucking parameter based on the deflection of the substrate.

Abstract: Methods for chucking and de-chucking a substrate from an electrostatic chucking (ESC) substrate support to reduce scratches of the non-active surface of a substrate include simultaneously increasing a voltage applied to a chucking electrode embedded in the ESC substrate support and a backside gas pressure in a backside volume disposed between the substrate and the substrate support to chuck the substrate and reversing the process to de-chuck the substrate.

Abstract: Methods of polishing a patterned surface of an electrostatic chucking (ESC) substrate support to be used in plasma assisted or plasma enhanced semiconductor manufacturing chambers are provided herein. In particular, embodiments described herein, provide polishing methods that round and debur the edges of elevated features and remove dielectric material from the non-substrate contacting surfaces of a patterned substrate support to reduce defectivity associated therewith.

Abstract: Methods for chucking and de-chucking a substrate from an electrostatic chucking (ESC) substrate support to reduce scratches of the non-active surface of a substrate include simultaneously increasing a voltage applied to a chucking electrode embedded in the ESC substrate support and a backside gas pressure in a backside volume disposed between the substrate and the substrate support to chuck the substrate and reversing the process to de-chuck the substrate.

Abstract: Methods of polishing a patterned surface of an electrostatic chucking (ESC) substrate support to be used in plasma assisted or plasma enhanced semiconductor manufacturing chambers are provided herein. In particular, embodiments described herein, provide polishing methods that round and debur the edges of elevated features and remove dielectric material from the non-substrate contacting surfaces of a patterned substrate support to reduce defectivity associated therewith.

Abstract: Methods for chucking and de-chucking a substrate from an electrostatic chucking (ESC) substrate support to reduce scratches of the non-active surface of a substrate include simultaneously increasing a voltage applied to a chucking electrode embedded in the ESC substrate support and a backside gas pressure in a backside volume disposed between the substrate and the substrate support to chuck the substrate and reversing the process to de-chuck the substrate.

Abstract: Embodiments described herein provide methods and apparatus used to reduce or substantially eliminate undesirable scratches to the non-active surface of a substrate by monitoring and controlling the deflection of a substrate, and thus the contact force between the substrate and a substrate support, during substrate processing. In one embodiment a method for processing a substrate includes positioning the substrate on a patterned surface of a substrate support, where the substrate support is disposed in a processing volume of a processing chamber, applying a chucking voltage to a chucking electrode disposed in the substrate support; flowing a gas into a backside volume disposed between the substrate and the substrate support, monitoring a deflection of the substrate, and changing a chucking parameter based on the deflection of the substrate.

Abstract: Methods for removing contamination from a surface disposed in a substrate processing system are provided herein. In some embodiments, a method for removing contaminants from a surface includes: providing a first process gas comprising a chlorine containing gas, a hydrogen containing gas, and an inert gas to a process chamber having the surface disposed within the process chamber; igniting the first process gas to form a plasma from the first process gas; and exposing the surface to the plasma to remove contaminants from the surface. In some embodiments, the surface is an exposed surface of a process chamber component. In some embodiments, the surface is a surface of a first layer disposed atop a substrate, such as a semiconductor wafer.

Abstract: Methods for surface interface engineering in semiconductor fabrication are provided herein. In some embodiments, a method of processing a substrate disposed atop a substrate support in a processing volume of a processing chamber includes: generating an ion species from an inductively coupled plasma formed within the processing volume of the processing chamber from a first process gas; exposing a first layer of the substrate to the ion species to form an ammonium fluoride (NH4F) film atop the first layer, wherein the first layer comprises silicon oxide; and heating the substrate to a second temperature at which the ammonium fluoride film reacts with the first layer to selectively etch the silicon oxide.

Abstract: Methods for removing contamination from a surface disposed in a substrate processing system are provided herein. In some embodiments, a method for removing contaminants from a surface includes: providing a first process gas comprising a chlorine containing gas, a hydrogen containing gas, and an inert gas to a process chamber having the surface disposed within the process chamber; igniting the first process gas to form a plasma from the first process gas; and exposing the surface to the plasma to remove contaminants from the surface. In some embodiments, the surface is an exposed surface of a process chamber component. In some embodiments, the surface is a surface of a first layer disposed atop a substrate, such as a semiconductor wafer.

Abstract: Methods for surface interface engineering in semiconductor fabrication are provided herein. In some embodiments, a method of processing a substrate disposed atop a substrate support in a processing volume of a processing chamber includes: generating an ion species from an inductively coupled plasma formed within the processing volume of the processing chamber from a first process gas; exposing a first layer of the substrate to the ion species to form an ammonium fluoride (NH4F) film atop the first layer, wherein the first layer comprises silicon oxide; and heating the substrate to a second temperature at which the ammonium fluoride film reacts with the first layer to selectively etch the silicon oxide.

Abstract: Embodiments of the invention provide a method and apparatus, such as a processing chamber, suitable for etching high aspect ratio features. Other embodiments include a showerhead assembly for use in the processing chamber. In one embodiment, a processing chamber includes a chamber body having a showerhead assembly and substrate support disposed therein. The showerhead assembly includes at least two fluidly isolated plenums, a region transmissive to an optical metrology signal, and a plurality of gas passages formed through the showerhead assembly fluidly coupling the plenums to the interior volume of the chamber body.

Abstract: A method of etching a substrate is provided. The method of etching a substrate includes transferring a pattern into the substrate using a double patterned amorphous carbon layer on the substrate as a hardmask. Optionally, a non-carbon based layer is deposited on the amorphous carbon layer as a capping layer before the pattern is transferred into the substrate.

Abstract: A method of etching a substrate is provided. The method of etching a substrate includes transferring a pattern into the substrate using a double patterned amorphous carbon layer on the substrate as a hardmask. Optionally, a non-carbon based layer is deposited on the amorphous carbon layer as a capping layer before the pattern is transferred into the substrate.

Abstract: The present invention includes a method for patterning a bilayer resist having a patterned upper resist layer over a lower resist layer formed on a substrate. In one embodiment of the present invention, the method includes an optional upper resist layer trimming step, an upper resist layer treatment step, and a lower resist layer etching step. In the upper resist layer trimming step, the upper resist layer is trimmed in a plasma of a first process gas. In the upper resist layer treatment step, the upper resist layer is treated in a plasma of a second process gas to increase its etch resistance during the subsequent lower resist layer etching step. In the lower resist etching step, the lower resist layer is etched in a plasma of a third process gas, using the upper resist layer as a mask.