Abstract: A semiconductor device includes a substrate including a first side and a second side opposite to each other, a first penetrating structure that penetrates the substrate, and a second penetrating structure that penetrates the substrate, the second penetrating structure being spaced apart from the first penetrating structure, and an area of the first penetrating structure being more than twice an area of the second penetrating structure, as viewed from the first side of the substrate.

Abstract: A steering device for an OHT according to some example embodiments of the present inventive concepts includes: an LM block; a steering plate fixedly installed to the LM block and provided with an insertion groove; a link installed in the insertion groove of the steering plate and tilted; a main bearing having an outer circumferential surface in contact with the link to reduce friction when the link is tilted; and a guide roller rotatably installed on a protrusion protruding from the link.

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

Abstract: A thermal pad of a semiconductor chip, a semiconductor chip including the thermal pad, and a method of manufacturing the semiconductor chip, the thermal pad including a thermal core in a trench at a lower surface of a semiconductor substrate, the thermal core being configured to receive heat generated from a through silicon via (TSV) vertically extending through the semiconductor substrate; a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core; a first insulation layer between an inner surface of the trench and the thermal core; and a second insulation layer between the first insulation layer and the thermal core.

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

Abstract: A thermal pad of a semiconductor chip, a semiconductor chip including the thermal pad, and a method of manufacturing the semiconductor chip, the thermal pad including a thermal core in a trench at a lower surface of a semiconductor substrate, the thermal core being configured to receive heat generated from a through silicon via (TSV) vertically extending through the semiconductor substrate; a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core; a first insulation layer between an inner surface of the trench and the thermal core; and a second insulation layer between the first insulation layer and the thermal core.

Abstract: A semiconductor device includes an insulating structure on a semiconductor substrate, lower conductive patterns in the insulating structure, upper conductive patterns on the insulating structure, conductive vias in the insulating structure and connecting at least one of the upper conductive patterns to at least one of the lower conductive patterns, a protective layer covering the insulating structure and the upper conductive patterns, an etch stop layer covering the protective layer, a first passivation layer on portions of the etch stop layer between the upper conductive patterns, and an upper passivation layer on the first passivation layer.

Abstract: A semiconductor device includes an interlayer insulating layer, a first protective insulating layer on the interlayer insulating layer, a second protective insulating layer on the first protective insulating layer, and insulating structures disposed in at least one of the first protective insulating layer or the second protective insulating layer, wherein the insulating structures include a first insulating structure including a first material having a first physical property, and a second insulating structure including a second material having a second physical property, and the first material and the second material include a same material, and the first physical property and the second physical property are different physical properties.

Abstract: A detection pad structure in a semiconductor device may include a lower wiring on a substrate, an upper wiring on the lower wiring, and a first pad pattern on the upper wiring. The upper wiring may be connected to the lower wiring and include metal patterns and via contacts on the metal patterns that are stacked in a plurality of layers. The first pad pattern may be connected to the upper wiring. A semiconductor device may include an actual upper wiring including actual metal patterns and actual via contacts stacked in a plurality of layers. At least one of the metal patterns of each layer in the upper wiring may have a minimum line width and a minimum space of the metal patterns of each layer in the actual upper wiring. Metal patterns and via contacts of each layer in the upper wiring may be regularly and repeatedly arranged.

Abstract: An autonomous driving robot includes a storage unit including a housing, which provides a space for storing an article, and a shelf which is provided inside the housing and on which the article is loaded, a manipulator including a linear actuator, and a selective compliance articulated robot arm, which is coupled to the linear actuator, and a transport unit coupled to the storage unit, wherein a plurality of shelves are provided, some of the shelves are provided adjacent to one inner wall of the housing and spaced apart from each other in the vertical direction, and the other shelves are provided adjacent to another inner wall which faces the one inner wall and spaced apart from each other in the vertical direction, and the plurality of shelves extend toward a central portion of the housing, but extend to a point before reaching the central portion of the housing.

Abstract: A semiconductor chip includes a semiconductor substrate including an active surface and an inactive surface facing the active surface, a multi wiring layer arranged on the active surface of the semiconductor substrate, and including a wiring structure having at least two layers and including a conductive wiring and a dummy wiring, a lower protection layer arranged on a front surface of the multi wiring layer, and including a conductive medium pad connected to the conductive wiring, a plurality of through vias configured to penetrate the semiconductor substrate, and including a plurality of power through vias, a plurality of signal through vias, and a plurality of dummy through vias; and a plurality of back side pads arranged on the inactive surface of the semiconductor substrate, and connected to the plurality of through vias, wherein the plurality of dummy through vias are connected to the wiring structure.

Abstract: An apparatus for storage of a carrying material, includes: a body frame; a plurality of loading members installed on the body frame and disposed such that a carrying material forms a plurality of layers in upper and lower directions; a driving unit connected to at least one of the plurality of loading members; and an auxiliary coupling unit provided in a portion of the plurality of loading members for attachment and detachment to and from a neighboring loading member, wherein the plurality of loading members are provided with a plurality of first loading members fixedly installed at a lower end portion of the body frame, and a plurality of second loading members disposed above the first loading member and movably installed on the body frame, wherein the driving unit is connected to at least one of the plurality of second loading members, wherein the auxiliary coupling unit includes an electromagnet installed at one end of the second loading members, and a magnetic body installed at the other end of the second

Abstract: A semiconductor package includes a first semiconductor chip including a circuit layer on a first substrate, first through silicon vias passing through the first substrate, first lower bump pads on the circuit layer, and a first upper bump pad and a second upper bump pad on a second surface of the first substrate, each of the first upper bump pad and the second upper bump pad connected to a corresponding one of the first through silicon vias. The package includes a second semiconductor chip including a circuit layer on a first surface of a second substrate, and second lower bump pads on the circuit layer on the second substrate. The package includes a first solder bump to bond the first upper bump pad and the second lower bump pad, and a plurality of second solder bumps to bond the second upper bump pad and the second lower bump pads.

Abstract: A semiconductor package, includes: a base chip having a front surface and a back surface opposite to the front surface, the base chip including bump pads, wafer test pads, and package test pads, disposed on the front surface; connection structures disposed on the front surface of the base chip and connected to the bump pads; and semiconductor chips stacked on the back surface of the base chip, wherein each of the wafer test pads is smaller than the package test pads.

Abstract: A semiconductor package includes a plurality of first semiconductor chips sequentially stacked, each of the first semiconductor chips including a circuit layer on a first surface of a first substrate, a through-silicon via passing through the first substrate, and a bump pad connected to the through-silicon via, and a second semiconductor chip on an uppermost first semiconductor chip, the second semiconductor chip including a circuit layer on a first surface of a second substrate, and a thermal path via in the second substrate.

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

Abstract: Provided are a semiconductor chip with a reduced thickness and improved reliability, and a semiconductor package including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, an integrated device layer on the semiconductor substrate, a multi-wiring layer on the integrated device layer, and a pad metal layer of a plurality of pad metal layers on the multi-wiring layer, and having test pads defined therein. The pad metal layers extend in a first direction parallel to a top surface of the semiconductor substrate or in a second direction perpendicular to the first direction. A test pad is a central portion of the pad metal layer and, and an outer portion of the pad metal layer excluding the test pad overlaps the wires in a third direction perpendicular to the top surface of the semiconductor substrate.

Abstract: A semiconductor device may include lower metal wirings on a substrate, a first upper insulating interlayer on the lower metal wirings, a first upper wiring including a first upper via in the first upper insulating interlayer and a first upper metal pattern on the first upper insulating interlayer. The semiconductor device may also include a second upper insulating interlayer on the first upper insulating interlayer, an uppermost wiring including an uppermost via in the second upper insulating interlayer, an uppermost metal pattern on the second upper insulating interlayer, and an oxide layer for supplying hydrogen on the second upper insulating interlayer. The lower metal wirings may be stacked in a plurality of layers. The oxide layer for supplying hydrogen may cover the uppermost wiring. A thickness of the uppermost via may be less than 40% of a thickness of the uppermost metal pattern.

Abstract: A semiconductor device may include a plurality of chip regions on a substrate, at least one scribe lane surrounding each of the plurality of chip regions on the substrate, a plurality of first align key patterns and a plurality of first test element group patterns included in the plurality of chip regions, and a plurality of second align key patterns and a plurality of second test element group patterns included in the at least one scribe lane.

Abstract: A storage system includes a storage device and a transfer device. The storage device includes a guide bar, a plurality of upper shelves connected to the guide bar, the plurality of upper shelves storing a material to be transferred, a plurality of lower shelves disposed under the plurality of upper shelves, the plurality of lower shelves storing the material, a plurality of guides connected to the plurality of upper shelves, and a shelf returning device connected to a selected upper shelf from among the plurality of upper shelves. The transfer device includes a body, a drive module attached to the body, the drive module moving the transfer device to be adjacent to the storage device, a handling module attached to the body, the handling module handling the material, and a shelf moving module attached to the body or the handling module, the shelf moving module contacting a selected guide from among the plurality of guides.