Patents by Inventor Jimin Zhu

Jimin Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240119147
    Abstract: A method in one embodiment creates a model of an authentic IC for use in comparisons with counterfeit ICs. The model can be created by determining a first or initial set of points of interest (POIs) on the simulated physical (e.g., gate level) layout and simulating side channel leakage from each POI and then expanding the size of the POI and repeating the simulation and comparing successive simulation results (between successive sizes of POIs for a given POI) to determine if a solution for the size of the POI has converged. The final POIs are then processed in a simulation that can use multiple payloads (e.g., cryptographic data) over the entire set of final POIs, and the resulting data set can be used to create the model.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Inventors: Deqi Zhu, Hua Chen, Jimin Wen, Lang Lin, Norman Chang, Dinesh Selvakumaran, Gang Ni
  • Publication number: 20240078362
    Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 7, 2024
    Inventors: Norman CHANG, Hsiming PAN, Jimin WEN, Deqi ZHU, Wenbo XIA, Akhilesh KUMAR, Wen-Tze CHUANG, En-Cih YANG, Karthik SRINIVASAN, Ying-Shiun LI
  • Patent number: 11914931
    Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. The methods can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC); performing a thermal simulation for each respective template of the IC based on a sequence of power patterns of tiles of the respective template; and training a neural network with a plurality of training data collected via thermal simulations performed for the templates of the IC. These systems and methods can use a machine learning predictor, that has been trained to determine a transient temperature rise across an entire IC, and then append the determined transient temperature rise to a system level thermal profile of the IC.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: February 27, 2024
    Assignee: ANSYS, INC.
    Inventors: Akhilesh Kumar, Norman Chang, Hsiming Pan, Jimin Wen, Deqi Zhu, Wenbo Xia, Wen-Tze Chuang, En-Cih Yang, Karthik Srinivasan, Ying-Shiun Li
  • Patent number: 10031516
    Abstract: A method for automatically collecting semiconductor manufacturing parameters of a manufacturing equipment is provided. The method includes reporting semiconductor manufacturing parameters obtained by self-monitoring of the manufacturing equipment and obtaining storage locations in an electronic data capture corresponding to reported semiconductor manufacturing parameters and transporting the reported semiconductor manufacturing parameters and corresponding storage locations. The method further includes receiving the reported semiconductor manufacturing parameters and the corresponding storage location and storing each reported semiconductor manufacturing parameters automatically into the electronic data capture of a manufacturing execution system according to the corresponding storage location.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: July 24, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Ke Xiao, Jimin Zhu, Lunguo Wang, Yunfei Sui, Xueqing Gao
  • Publication number: 20150287621
    Abstract: A method for automatically collecting semiconductor manufacturing parameters of a manufacturing equipment is provided. The method includes reporting semiconductor manufacturing parameters obtained by self-monitoring of the manufacturing equipment and obtaining storage locations in an electronic data capture corresponding to reported semiconductor manufacturing parameters and transporting the reported semiconductor manufacturing parameters and corresponding storage locations. The method further includes receiving the reported semiconductor manufacturing parameters and the corresponding storage location and storing each reported semiconductor manufacturing parameters automatically into the electronic data capture of a manufacturing execution system according to the corresponding storage location.
    Type: Application
    Filed: March 27, 2015
    Publication date: October 8, 2015
    Inventors: KE XIAO, JIMIN ZHU, LUNGUO WANG, YUNFEI SUI, XUEQING GAO
  • Publication number: 20120308444
    Abstract: In accordance with at least some embodiments of the present disclosure, a lateral flow immunoassay strip may include a first conjugate pad containing streptavidin-gold nanoparticle (streptavidin-AuNP) conjugates, a second conjugate pad containing anti-cardiac troponin I monoclonal antibody (anti-cTnI mAb)-AuNP-biotinylated single stranded DNA (ssDNA) conjugate complexes, and a nitrocellulose membrane coupled with the first conjugate pad and the second conjugate pad, wherein the nitrocellulose membrane contains a first test line prepared with capturing anti-cTnI mAb.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 6, 2012
    Inventor: Jimin Zhu